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Searched refs:ValueTypeByHwMode (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/utils/TableGen/
DInfoByHwMode.cpp32 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) { in ValueTypeByHwMode() function in ValueTypeByHwMode
41 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, MVT T) : ValueTypeByHwMode(T) { in ValueTypeByHwMode() function in ValueTypeByHwMode
46 bool ValueTypeByHwMode::operator== (const ValueTypeByHwMode &T) const { in operator ==()
57 bool ValueTypeByHwMode::operator< (const ValueTypeByHwMode &T) const { in operator <()
63 MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) { in getOrCreateTypeForMode()
76 StringRef ValueTypeByHwMode::getMVTName(MVT T) { in getMVTName()
82 void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const { in writeToStream()
105 void ValueTypeByHwMode::dump() const { in dump()
109 ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec, in getValueTypeByHwMode()
118 return ValueTypeByHwMode(Rec, CGH); in getValueTypeByHwMode()
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DInfoByHwMode.h120 struct ValueTypeByHwMode : public InfoByHwMode<MVT> { struct
121 ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
122 ValueTypeByHwMode(Record *R, MVT T);
123 ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode,T}); } in ValueTypeByHwMode() function
124 ValueTypeByHwMode() = default;
126 bool operator== (const ValueTypeByHwMode &T) const;
127 bool operator< (const ValueTypeByHwMode &T) const;
145 ValueTypeByHwMode getValueTypeByHwMode(Record *Rec, argument
183 raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
DCodeGenTarget.h55 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
113 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
131 std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
133 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const { in getLegalValueTypes()
DCodeGenDAGPatterns.h197 : TypeSetByHwMode(ValueTypeByHwMode(VT)) {} in TypeSetByHwMode()
198 TypeSetByHwMode(ValueTypeByHwMode VT) in TypeSetByHwMode()
199 : TypeSetByHwMode(ArrayRef<ValueTypeByHwMode>(&VT, 1)) {} in TypeSetByHwMode()
200 TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList);
209 ValueTypeByHwMode getValueTypeByHwMode() const;
238 bool insert(const ValueTypeByHwMode &VVT);
267 ValueTypeByHwMode getConcrete(const TypeSetByHwMode &VTS, in getConcrete()
281 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) { in MergeInTypeInfo()
311 const ValueTypeByHwMode &VVT);
412 ValueTypeByHwMode VVT;
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DCodeGenRegisters.h329 SmallVector<ValueTypeByHwMode, 4> VTs;
352 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; } in getValueTypes()
355 bool hasType(const ValueTypeByHwMode &VT) const { in hasType()
359 const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const { in getValueTypeNum()
736 getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr);
DCodeGenTarget.cpp344 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, in getSuperRegForSubReg()
360 [&ValueTy](const ValueTypeByHwMode &ClassVT) { in getSuperRegForSubReg()
405 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) in getRegisterVTs()
408 std::vector<ValueTypeByHwMode> Result; in getRegisterVTs()
411 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); in getRegisterVTs()
DDAGISelMatcherGen.cpp35 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0); in getRegisterValueType()
43 const ValueTypeByHwMode &T = RC.getValueTypeNum(0); in getRegisterValueType()
DCodeGenDAGPatterns.cpp70 TypeSetByHwMode::TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList) { in TypeSetByHwMode()
71 for (const ValueTypeByHwMode &VVT : VTList) { in TypeSetByHwMode()
87 ValueTypeByHwMode TypeSetByHwMode::getValueTypeByHwMode() const { in getValueTypeByHwMode()
90 ValueTypeByHwMode VVT; in getValueTypeByHwMode()
109 bool TypeSetByHwMode::insert(const ValueTypeByHwMode &VVT) { in insert()
209 OS << ValueTypeByHwMode::getMVTName(Types[i]); in writeToStream()
609 const ValueTypeByHwMode &VVT) { in EnforceVectorEltTypeIs()
2388 ValueTypeByHwMode VVT = TP.getInfer().getConcrete(Types[0], false); in ApplyTypeConstraints()
DRegisterInfoEmitter.cpp1248 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1298 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
DCodeGenInstruction.cpp463 const std::vector<ValueTypeByHwMode> &RegVTs = in HasOneImplicitDefWithKnownVT()
DFastISelEmitter.cpp173 ValueTypeByHwMode VVT = TP->getTree(0)->getType(0); in emitImmediatePredicate()
DCodeGenRegisters.cpp2392 ValueTypeByHwMode *VT) { in getMinimalPhysRegClass()
DGlobalISelEmitter.cpp4250 ValueTypeByHwMode VT = ChildTypes.front().getValueTypeByHwMode(); in importChildMatcher()
4288 ValueTypeByHwMode VTy = ChildTypes.front().getValueTypeByHwMode(); in importChildMatcher()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td285 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
287 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
289 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
291 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
294 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
296 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
298 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
301 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
303 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
305 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td321 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
323 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
325 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
327 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
330 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
332 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
334 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
337 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
339 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
341 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
/external/llvm-project/llvm/test/TableGen/
DHwModeSelect.td24 def BadDef : ValueTypeByHwMode<[TestMode1, TestMode2, DefaultMode],
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td86 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td109 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td52 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
/external/llvm-project/llvm/include/llvm/Target/
DTarget.td52 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>