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Searched refs:X86 (Results 1 – 25 of 1641) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenEVEX2VEXTables.inc3 |* X86 EVEX2VEX tables *|
9 // X86 EVEX encoded instructions that have a VEX 128 encoding
13 { X86::VADDPDZ128rm, X86::VADDPDrm },
14 { X86::VADDPDZ128rr, X86::VADDPDrr },
15 { X86::VADDPSZ128rm, X86::VADDPSrm },
16 { X86::VADDPSZ128rr, X86::VADDPSrr },
17 { X86::VADDSDZrm, X86::VADDSDrm },
18 { X86::VADDSDZrm_Int, X86::VADDSDrm_Int },
19 { X86::VADDSDZrr, X86::VADDSDrr },
20 { X86::VADDSDZrr_Int, X86::VADDSDrr_Int },
[all …]
DX86GenRegisterInfo.inc18 namespace X86 {
305 } // end namespace X86
309 namespace X86 {
431 } // end namespace X86
436 namespace X86 {
451 } // end namespace X86
1147 { X86::AH },
1148 { X86::AL },
1149 { X86::BH },
1150 { X86::BL },
[all …]
DX86GenRegisterBank.inc12 namespace X86 {
18 } // end namespace X86
35 namespace X86 {
38 (1u << (X86::GR8RegClassID - 0)) |
39 (1u << (X86::GR16RegClassID - 0)) |
40 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
41 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
42 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
43 (1u << (X86::GR8_NOREXRegClassID - 0)) |
44 (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrFoldTables.cpp36 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
37 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
38 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
39 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
40 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
41 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
42 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
43 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
44 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
45 { X86::ADD8ri_DB, X86::ADD8mi, TB_NO_REVERSE },
[all …]
DX86InstrInfo.cpp80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
81 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
83 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
84 X86::CATCHRET, in X86InstrInfo()
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)), in X86InstrInfo()
95 case X86::MOVSX16rr8: in isCoalescableExtInstr()
96 case X86::MOVZX16rr8: in isCoalescableExtInstr()
97 case X86::MOVSX32rr8: in isCoalescableExtInstr()
98 case X86::MOVZX32rr8: in isCoalescableExtInstr()
[all …]
DX86MCInstLower.cpp330 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
348 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
349 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
350 NewOpcode = X86::CBW; in SimplifyMOVSX()
352 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
353 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
354 NewOpcode = X86::CWDE; in SimplifyMOVSX()
356 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
357 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
358 NewOpcode = X86::CDQE; in SimplifyMOVSX()
[all …]
DX86FloatingPoint.cpp131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
133 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
251 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
295 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
296 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
318 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
319 return Reg - X86::FP0; in getFPReg()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFoldTables.cpp36 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
37 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
38 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
39 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
40 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
41 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
42 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
43 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
44 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
45 { X86::ADD8ri_DB, X86::ADD8mi, TB_NO_REVERSE },
[all …]
DX86InstrInfo.cpp80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
81 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
83 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
84 X86::CATCHRET, in X86InstrInfo()
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)), in X86InstrInfo()
95 case X86::MOVSX16rr8: in isCoalescableExtInstr()
96 case X86::MOVZX16rr8: in isCoalescableExtInstr()
97 case X86::MOVSX32rr8: in isCoalescableExtInstr()
98 case X86::MOVZX32rr8: in isCoalescableExtInstr()
[all …]
DX86MCInstLower.cpp303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
322 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
323 NewOpcode = X86::CBW; in SimplifyMOVSX()
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
326 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
327 NewOpcode = X86::CWDE; in SimplifyMOVSX()
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
330 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
331 NewOpcode = X86::CDQE; in SimplifyMOVSX()
[all …]
DX86FloatingPoint.cpp131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
133 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
251 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
295 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
296 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
318 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
319 return Reg - X86::FP0; in getFPReg()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
117 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
119 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
120 X86::CATCHRET, in X86InstrInfo()
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)), in X86InstrInfo()
125 { X86::ADC32ri, X86::ADC32mi, 0 }, in X86InstrInfo()
126 { X86::ADC32ri8, X86::ADC32mi8, 0 }, in X86InstrInfo()
127 { X86::ADC32rr, X86::ADC32mr, 0 }, in X86InstrInfo()
128 { X86::ADC64ri32, X86::ADC64mi32, 0 }, in X86InstrInfo()
[all …]
DX86FloatingPoint.cpp129 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6) in calcLiveInMask()
131 Mask |= 1 << (LI.PhysReg - X86::FP0); in calcLiveInMask()
197 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
226 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
236 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
280 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
281 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
296 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
297 return Reg - X86::FP0; in getFPReg()
308 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!"); in runOnMachineFunction()
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp70 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, in initLLVMToSEHAndCVRegMapping()
78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping()
79 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, in initLLVMToSEHAndCVRegMapping()
80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, in initLLVMToSEHAndCVRegMapping()
86 MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); in initLLVMToSEHAndCVRegMapping()
91 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); in initLLVMToSEHAndCVRegMapping()
96 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); in initLLVMToSEHAndCVRegMapping()
101 MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); in initLLVMToSEHAndCVRegMapping()
108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, in initLLVMToSEHAndCVRegMapping()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86InstPrinterCommon.cpp110 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
111 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
112 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
113 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
114 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
115 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
116 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
117 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; in printVPCOMMnemonic()
129 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: in printVPCMPMnemonic()
130 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: in printVPCMPMnemonic()
[all …]
DX86MCTargetDesc.cpp74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
79 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
89 {codeview::RegisterId::AL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
90 {codeview::RegisterId::CL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
91 {codeview::RegisterId::DL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
92 {codeview::RegisterId::BL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
93 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
94 {codeview::RegisterId::CH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
95 {codeview::RegisterId::DH, X86::DH}, in initLLVMToSEHAndCVRegMapping()
96 {codeview::RegisterId::BH, X86::BH}, in initLLVMToSEHAndCVRegMapping()
[all …]
DX86ATTInstPrinter.cpp56 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
57 (STI.getFeatureBits()[X86::Mode64Bit])) { in printInst()
66 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
67 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
92 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
93 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
94 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
95 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
96 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
97 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
[all …]
DX86IntelInstPrinter.cpp45 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
46 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
75 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
76 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
77 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
[all …]
DX86BaseInfo.h26 namespace X86 {
139 case X86::TEST16i16: in classifyFirstOpcodeInMacroFusion()
140 case X86::TEST16mr: in classifyFirstOpcodeInMacroFusion()
141 case X86::TEST16ri: in classifyFirstOpcodeInMacroFusion()
142 case X86::TEST16rr: in classifyFirstOpcodeInMacroFusion()
143 case X86::TEST32i32: in classifyFirstOpcodeInMacroFusion()
144 case X86::TEST32mr: in classifyFirstOpcodeInMacroFusion()
145 case X86::TEST32ri: in classifyFirstOpcodeInMacroFusion()
146 case X86::TEST32rr: in classifyFirstOpcodeInMacroFusion()
147 case X86::TEST64i32: in classifyFirstOpcodeInMacroFusion()
[all …]
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86InstPrinterCommon.cpp111 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
112 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
113 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
114 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
115 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
116 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
117 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
118 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; in printVPCOMMnemonic()
130 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: in printVPCMPMnemonic()
131 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: in printVPCMPMnemonic()
[all …]
DX86MCTargetDesc.cpp72 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
77 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
87 {codeview::RegisterId::AL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
88 {codeview::RegisterId::CL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
89 {codeview::RegisterId::DL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
90 {codeview::RegisterId::BL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
91 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
92 {codeview::RegisterId::CH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
93 {codeview::RegisterId::DH, X86::DH}, in initLLVMToSEHAndCVRegMapping()
94 {codeview::RegisterId::BH, X86::BH}, in initLLVMToSEHAndCVRegMapping()
[all …]
DX86ATTInstPrinter.cpp57 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
58 (STI.getFeatureBits()[X86::Mode64Bit])) { in printInst()
67 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
68 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
92 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
93 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
94 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
95 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
96 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
97 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
[all …]
DX86IntelInstPrinter.cpp46 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
47 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
75 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
76 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
77 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
[all …]
/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp112 namespace X86 { namespace
157 if (FB[X86::Mode16Bit]) { in X86GenericDisassembler()
160 } else if (FB[X86::Mode32Bit]) { in X86GenericDisassembler()
163 } else if (FB[X86::Mode64Bit]) { in X86GenericDisassembler()
249 #define ENTRY(x) X86::x, in translateRegister()
302 X86::CS,
303 X86::SS,
304 X86::DS,
305 X86::ES,
306 X86::FS,
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Datomic-idempotent.ll3 …-machineinstrs -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-GENERIC,X86-SSE2
4 …y-machineinstrs -mcpu=slm -mattr=-sse2 | FileCheck %s --check-prefixes=X86,X86-GENERIC,X86-SLM
5 …y-machineinstrs -mcpu=goldmont -mattr=-sse2 | FileCheck %s --check-prefixes=X86,X86-GENERIC,X86-SLM
6 …y-machineinstrs -mcpu=knl -mattr=-sse2 | FileCheck %s --check-prefixes=X86,X86-GENERIC,X86-SLM
7 …86-- -verify-machineinstrs -mcpu=atom -mattr=-sse2 | FileCheck %s --check-prefixes=X86,X86-ATOM
21 ; X86-SSE2-LABEL: add8:
22 ; X86-SSE2: # %bb.0:
23 ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
24 ; X86-SSE2-NEXT: mfence
25 ; X86-SSE2-NEXT: movb (%eax), %al
[all …]

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