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/external/llvm-project/llvm/test/CodeGen/X86/
Dmemset.ll4 ; RUN: llc < %s -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
38 ; YMM-LABEL: t:
39 ; YMM: ## %bb.0: ## %entry
40 ; YMM-NEXT: pushl %ebp
41 ; YMM-NEXT: movl %esp, %ebp
42 ; YMM-NEXT: andl $-32, %esp
43 ; YMM-NEXT: subl $96, %esp
44 ; YMM-NEXT: leal {{[0-9]+}}(%esp), %eax
45 ; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
46 ; YMM-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
[all …]
Davx512f-256-set0.mir4 # Test that we emit VPXORD with ZMM registers instead of YMM
/external/llvm-project/llvm/lib/Target/X86/
DX86Schedule.td85 X86FoldableSchedWrite YMM = s256; // YMM operations.
119 X86SchedWriteMoveLS YMM = s256; // YMM operations.
239 defm WriteFAddY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (YMM).
243 defm WriteFAdd64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (YMM).
247 defm WriteFCmpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (YMM).
251 defm WriteFCmp64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (YMM).
257 defm WriteFMulY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
258 defm WriteFMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
261 …m WriteFMul64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (YMM).
265 defm WriteFDivY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (YMM).
[all …]
DX86SchedBroadwell.td247 defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
251 …BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
256 defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
260 …BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
268 …BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
272 …ResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
277 …teFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
281 …teFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
287 …SqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
292 …, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
[all …]
DX86InstrFMA.td113 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>,
116 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>,
119 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>,
504 VEX_W, VEX_L, Sched<[sched.YMM]>;
511 Sched<[sched.YMM.Folded, sched.YMM.ReadAfterFold, sched.YMM.ReadAfterFold]>;
518 Sched<[sched.YMM.Folded, sched.YMM.ReadAfterFold,
523 sched.YMM.ReadAfterFold]>;
535 VEX_L, Sched<[sched.YMM]>, FoldGenData<NAME#Yrr>;
DX86CallingConv.td35 list<Register> YMM = [];
47 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7];
54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
113 // __m256, __m256i, __m256d --> YMM
116 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
190 // __m256, __m256i, __m256d --> YMM
192 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
552 // The first 8 256-bit vector arguments are passed in YMM registers, unless
764 // AVX 256-bit vector arguments are passed in YMM registers.
783 // AVX 256-bit vector arguments are passed in YMM registers.
[all …]
DX86InstrSSE.td365 SSEPackedSingle, SchedWriteFMoveLS.YMM>,
368 SSEPackedDouble, SchedWriteFMoveLS.YMM>,
371 SSEPackedSingle, SchedWriteFMoveLS.YMM>,
374 SSEPackedDouble, SchedWriteFMoveLS.YMM>,
415 let SchedRW = [SchedWriteFMoveLS.YMM.MR] in {
457 let SchedRW = [SchedWriteFMoveLS.YMM.RR] in {
1532 // YMM only
1616 // YMM only
1944 SchedWriteFCmpSizes.PS.YMM, SSEPackedSingle, loadv8f32>, PS, VEX_4V, VEX_L, VEX_WIG;
1947 SchedWriteFCmpSizes.PD.YMM, SSEPackedDouble, loadv4f64>, PD, VEX_4V, VEX_L, VEX_WIG;
[all …]
DX86InstrXOP.td82 SchedWriteFRnd.YMM>;
91 SchedWriteFRnd.YMM>;
371 SchedWriteShuffle.YMM>, VEX_L;
462 SchedWriteFVarShuffle.YMM>, VEX_L;
471 SchedWriteFVarShuffle.YMM>, VEX_L;
DX86InstrAVX512.td1422 Sched<[SchedWriteShuffle.YMM.Folded]>,
1437 Sched<[SchedWriteShuffle.YMM.Folded]>,
2012 defm Z256 : WriteFVarBlendask<opc, OpcodeStr, sched.YMM, VTInfo.info256>,
2013 WriteFVarBlendask_rmb<opc, OpcodeStr, sched.YMM, VTInfo.info256>,
2028 defm Z256 : WriteFVarBlendask<opc, OpcodeStr, sched.YMM, VTInfo.info256>,
2189 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, sched.YMM,
2205 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, sched.YMM,
2370 sched.YMM, VTInfo.info256, NAME>, EVEX_V256;
2386 sched.YMM, VTInfo.info256, NAME>, EVEX_V256;
2639 defm Z256 : avx512_vcmp_common<sched.YMM, _.info256, NAME>, EVEX_V256;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86Schedule.td85 X86FoldableSchedWrite YMM = s256; // YMM operations.
119 X86SchedWriteMoveLS YMM = s256; // YMM operations.
239 defm WriteFAddY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (YMM).
243 defm WriteFAdd64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (YMM).
247 defm WriteFCmpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (YMM).
251 defm WriteFCmp64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (YMM).
256 defm WriteFMulY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
257 defm WriteFMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
260 …m WriteFMul64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (YMM).
264 defm WriteFDivY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (YMM).
[all …]
DX86SchedBroadwell.td247 defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
251 …BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
256 defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
260 …BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
267 …BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
271 …ResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
276 …teFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
280 …teFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
286 …SqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
291 …, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
[all …]
DX86InstrFMA.td113 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>,
116 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>,
119 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>,
504 VEX_W, VEX_L, Sched<[sched.YMM]>;
511 Sched<[sched.YMM.Folded, sched.YMM.ReadAfterFold, sched.YMM.ReadAfterFold]>;
518 Sched<[sched.YMM.Folded, sched.YMM.ReadAfterFold,
523 sched.YMM.ReadAfterFold]>;
535 VEX_L, Sched<[sched.YMM]>, FoldGenData<NAME#Yrr>;
DX86CallingConv.td35 list<Register> YMM = [];
47 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7];
54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
113 // __m256, __m256i, __m256d --> YMM
116 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
190 // __m256, __m256i, __m256d --> YMM
192 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
546 // The first 8 256-bit vector arguments are passed in YMM registers, unless
758 // AVX 256-bit vector arguments are passed in YMM registers.
777 // AVX 256-bit vector arguments are passed in YMM registers.
[all …]
DX86InstrSSE.td365 SSEPackedSingle, SchedWriteFMoveLS.YMM>,
368 SSEPackedDouble, SchedWriteFMoveLS.YMM>,
371 SSEPackedSingle, SchedWriteFMoveLS.YMM>,
374 SSEPackedDouble, SchedWriteFMoveLS.YMM>,
415 let SchedRW = [SchedWriteFMoveLS.YMM.MR] in {
457 let SchedRW = [SchedWriteFMoveLS.YMM.RR] in {
1495 // YMM only
1579 // YMM only
1939 SchedWriteFCmpSizes.PS.YMM, SSEPackedSingle, loadv8f32>, PS, VEX_4V, VEX_L, VEX_WIG;
1942 SchedWriteFCmpSizes.PD.YMM, SSEPackedDouble, loadv4f64>, PD, VEX_4V, VEX_L, VEX_WIG;
[all …]
DX86InstrXOP.td82 SchedWriteFRnd.YMM>;
91 SchedWriteFRnd.YMM>;
371 SchedWriteShuffle.YMM>, VEX_L;
462 SchedWriteFVarShuffle.YMM>, VEX_L;
471 SchedWriteFVarShuffle.YMM>, VEX_L;
DX86InstrAVX512.td1376 Sched<[SchedWriteShuffle.YMM.Folded]>,
1391 Sched<[SchedWriteShuffle.YMM.Folded]>,
2029 defm Z256 : WriteFVarBlendask<opc, OpcodeStr, sched.YMM, VTInfo.info256>,
2030 WriteFVarBlendask_rmb<opc, OpcodeStr, sched.YMM, VTInfo.info256>,
2045 defm Z256 : WriteFVarBlendask<opc, OpcodeStr, sched.YMM, VTInfo.info256>,
2206 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, sched.YMM,
2222 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, sched.YMM,
2387 sched.YMM, VTInfo.info256, NAME>, EVEX_V256;
2403 sched.YMM, VTInfo.info256, NAME>, EVEX_V256;
2608 defm Z256 : avx512_vcmp_common<sched.YMM, _.info256, NAME>, EVEX_V256;
[all …]
/external/llvm/test/CodeGen/X86/
Dmemset.ll3 …lc < %s -march=x86 -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
31 ; YMM: vxorps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, [[Z:%ymm[0-9]+]]
32 ; YMM: vmovaps [[Z]],
33 ; YMM-NOT: movaps
34 ; YMM: ret
/external/llvm-project/lldb/source/Plugins/Process/Utility/
DRegisterContext_x86.h303 struct YMM { struct
326 YMM = SSE << 1, enumerator
327 BNDREGS = YMM << 1,
DRegisterContextPOSIX_x86.h184 lldb_private::YMM m_ymm_set; // copy of ymmh and xmm register halves.
/external/llvm/lib/Target/X86/
DX86CallingConv.td335 // The first 8 256-bit vector arguments are passed in YMM registers, unless
444 // 256-bit vectors use YMM registers.
535 // AVX 256-bit vector arguments are passed in YMM registers.
554 // AVX 256-bit vector arguments are passed in YMM registers.
666 // 256-bit vectors use YMM registers.
777 // The 256-bit vector arguments are passed in YMM registers.
886 (sequence "YMM%u", 0, 15))>;
897 (sequence "YMM%u", 0, 7))>;
904 (sequence "YMM%u", 0, 15)),
914 (sequence "YMM%u", 6, 15))>;
[all …]
DX86RegisterInfo.td215 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
223 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>,
472 256, (sequence "YMM%u", 0, 15)>;
481 256, (sequence "YMM%u", 0, 7)>;
483 256, (sequence "YMM%u", 8, 15)>;
508 256, (sequence "YMM%u", 0, 31)>;
/external/llvm-project/lldb/source/Plugins/Process/Linux/
DNativeRegisterContextLinux_x86_64.h102 YMM m_ymm_set;
/external/libjpeg-turbo/simd/x86_64/
Djsimdcpu.asm71 cmp rax, 6 ; O/S does not manage XMM/YMM state
/external/libjpeg-turbo/simd/i386/
Djsimdcpu.asm81 cmp eax, 6 ; O/S does not manage XMM/YMM state
/external/llvm-project/llvm/test/tools/llvm-mca/X86/BtVer2/
Dpipes-fpu.s16 # FPA/FPM YMM

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