| /external/libwebsockets/lib/core-net/ |
| D | pollfd.c | 28 _lws_change_pollfd(struct lws *wsi, int _and, int _or, struct lws_pollargs *pa) in _lws_change_pollfd() argument
50 !_and && _or == LWS_POLLOUT) { in _lws_change_pollfd()
115 ftp->_and = _and; in _lws_change_pollfd()
151 pa->fd, pfd->events, (pfd->events & ~_and) | _or); in _lws_change_pollfd()
153 pa->events = pfd->events = (pfd->events & ~_and) | _or; in _lws_change_pollfd()
170 if (_and & LWS_POLLIN) in _lws_change_pollfd()
178 if (_and & LWS_POLLOUT) in _lws_change_pollfd()
458 __lws_change_pollfd(struct lws *wsi, int _and, int _or) in __lws_change_pollfd() argument
479 ret = _lws_change_pollfd(wsi, _and, _or, &pa); in __lws_change_pollfd()
492 lws_change_pollfd(struct lws *wsi, int _and, int _or) in lws_change_pollfd() argument
[all …]
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| D | private-lib-core-net.h | 1035 lws_change_pollfd(struct lws *wsi, int _and, int _or);
1112 __lws_change_pollfd(struct lws *wsi, int _and, int _or);
1206 _lws_change_pollfd(struct lws *wsi, int _and, int _or, struct lws_pollargs *pa);
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 2432 _and(T3, T1, T2); in lowerAlloca()
2437 _and(T5, T4, AlignAmount); in lowerAlloca()
2486 _and(T_Lo, Src0LoR, Src1LoR); in lowerInt64Arithmetic()
2488 _and(T_Hi, Src0HiR, Src1HiR); in lowerInt64Arithmetic()
2823 _and(T, Src0R, Src1R); in lowerArithmetic()
4490 _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element in lowerInsertElement()
4499 _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element in lowerInsertElement()
4535 _and(Dest, Src0, Src1); in createArithInst()
4604 _and(T3, Base, T1); // Align the address in lowerIntrinsic()
4611 _and(Tdest, T6, SrcMask); in lowerIntrinsic()
[all …]
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| D | IceTargetLoweringX8632.cpp | 302 _and(JumpTarget, Ctx->getConstantInt32(~(BundleSize - 1))); in lowerIndirectJump()
366 _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1))); in emitCallToTarget()
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| D | IceTargetLoweringX8664.cpp | 633 _and(T, Ctx->getConstantInt32(~(BundleSize - 1))); in lowerIndirectJump()
698 _and(T, Ctx->getConstantInt32(~(BundleSize - 1))); in emitCallToTarget()
784 _and(T_ecx, Ctx->getConstantInt32(~(BundleSize - 1))); in emitSandboxedReturn()
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| D | IceTargetLoweringX86BaseImpl.h | 1209 _and(getPhysicalRegister(getStackReg(), Traits::WordType),
1536 _and(esp, Ctx->getConstantInt32(-Alignment));
1569 _and(T, Ctx->getConstantInt32(-Alignment));
2044 _and(T_Lo, Src1Lo);
2047 _and(T_Hi, Src1Hi);
2304 _and(T, Src1);
2536 _and(T, Ctx->getConstantInt(Ty, -(1 << LogDiv)));
3034 _and(T, Ctx->getConstantInt1(1));
3087 _and(T_2, Ctx->getConstantInt1(1));
3117 _and(T_2, Ctx->getConstantInt1(1));
[all …]
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| D | IceTargetLoweringARM32.cpp | 2373 _and(T, Src0, Src1RF); in lowerInt1Arithmetic()
2614 _and(T_Lo, Src0LoR, Src1LoRF); in lowerInt64Arithmetic()
2616 _and(T_Hi, Src0HiR, Src1HiRF); in lowerInt64Arithmetic()
3265 _and(T, Src0R, Src1RF); in lowerArithmetic()
3994 _and(T_Lo, T_Lo, _1); in lowerCast()
4010 _and(T, T, _1); in lowerCast()
4037 _and(T, T, Ctx->getConstantInt1(1)); in lowerCast()
6624 _and(Reg, Reg, Mask); in alignRegisterPow2()
6784 _and(T_Lo, T_Lo, _1); in lowerInt1ForSelect()
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| D | IceTargetLoweringMIPS32.h | 174 void _and(Variable *Dest, Variable *Src0, Variable *Src1) { in _and() function
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| D | IceTargetLoweringARM32.h | 343 void _and(Variable *Dest, Variable *Src0, Operand *Src1,
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| D | IceTargetLoweringX86Base.h | 543 void _and(Variable *Dest, Operand *Src0) { in _and() function
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| /external/skia/infra/bots/assets/ |
| D | README.md | 19 * [optional] create\_and\_upload.py: Convenience script which combines create.py with upload.py.
|
| /external/skqp/infra/bots/assets/ |
| D | README.md | 19 * [optional] create\_and\_upload.py: Convenience script which combines create.py with upload.py.
|
| /external/libwebsockets/lib/plat/unix/ |
| D | unix-service.c | 173 __lws_change_pollfd(wsi, ftp->_and, in _lws_plat_service_tsi()
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | fneg-fabs.f16.ll | 10 ; GFX89-NOT: _and
26 ; GFX89-NOT: _and
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| /external/libwebsockets/lib/core/ |
| D | private-lib-core.h | 241 int _and; member
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| /external/llvm-project/mlir/lib/Target/LLVMIR/ |
| D | ModuleTranslation.cpp | 259 case LLVM::AtomicBinOp::_and: in getLLVMAtomicBinOp()
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| /external/llvm-project/mlir/include/mlir/Dialect/LLVMIR/ |
| D | LLVMOps.td | 1104 def AtomicBinOpAnd : I64EnumAttrCase<"_and", 3>;
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| /external/llvm-project/mlir/test/Target/ |
| D | llvmir.mlir | 1123 %5 = llvm.atomicrmw _and %i32_ptr, %i32 acq_rel : !llvm.i32
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 5243 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5265 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5274 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
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| /external/python/cpython2/Doc/reference/ |
| D | expressions.rst | 1307 .. _and:
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| /external/python/cpython3/Doc/reference/ |
| D | expressions.rst | 1609 .. _and:
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| /external/llvm-project/clang/docs/ |
| D | ClangCommandLineReference.rst | 367 .. option:: -no\_dead\_strip\_inits\_and\_terms
|