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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;
98 def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>;
101 def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>;
239 def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>;
255 def : TLBI<"ASIDE1", 0b01, 0b000, 0b1000, 0b0111, 0b010>;
329 def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;
337 def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
351 def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> {
356 def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td59 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
116 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
118 def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>;
121 def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;
410 def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
426 def : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
441 def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
470 def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
472 def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
565 def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
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DAArch64SVEInstrInfo.td105 defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and", int_aarch64_sve_and>;
126 defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv", AArch64sminv_pred>;
130 defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv", AArch64andv_pred>;
143 defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", int_aarch64_sve_smulh>;
159 defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth", int_aarch64_sve_sxth>;
168 defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt", int_aarch64_sve_cnt>;
176 defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin", int_aarch64_sve_smin>;
186 defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
209 defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul", fmul>;
303 defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">;
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/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td64 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
121 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
123 def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>;
126 def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;
415 def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
431 def : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
446 def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
475 def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
477 def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
570 def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
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DAArch64SVEInstrInfo.td306 defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and", int_aarch64_sve_and>;
327 defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv", AArch64sminv_p>;
331 defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv", AArch64andv_p>;
344 …defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", "SMULH_ZPZZ", int_aarch64_sve_smulh, Des…
365 defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth", AArch64sxt_mt>;
374 defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt", int_aarch64_sve_cnt>;
387 …defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin", "SMIN_ZPZZ", int_aarch64_sve_smin, Destruc…
402 defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
447 defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul", fmul, AArch64fmul_p>;
631 defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas", null_frag>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td80 defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
81 defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
83 defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
85 defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
87 defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">,
89 defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">,
91 defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">,
93 defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">,
95 defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">,
97 defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
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DRISCVInstrInfoF.td106 def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
115 def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
154 def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">;
175 def FEQ_S : FPCmpS_rr<0b010, "feq.s">;
DRISCVInstrInfoM.td31 def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td80 defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
81 defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
83 defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
85 defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
87 defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">,
89 defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">,
91 defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">,
93 defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">,
95 defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">,
97 defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
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DRISCVInstrInfoF.td105 def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
114 def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
155 def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">,
179 def FEQ_S : FPCmpS_rr<0b010, "feq.s">;
DRISCVInstrInfoM.td31 def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
880 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
895 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
896 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
897 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
903 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
904 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
905 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
906 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
909 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
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DHexagonInstrInfoVector.td75 def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>;
76 def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>;
77 def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>;
81 def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>;
DHexagonInstrInfoV5.td34 def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>;
174 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
274 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
614 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
620 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
624 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
628 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
DHexagonInstrInfoV4.td140 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
187 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
621 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
714 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
789 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
1024 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1626 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1686 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1978 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1983 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
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DHexagonSystemInst.td74 "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td407 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
408 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
409 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
410 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
569 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
570 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
571 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
572 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
579 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
580 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
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/external/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td421 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
422 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
423 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
424 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
583 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
584 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
585 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
586 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
593 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
594 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td421 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
422 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
423 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
424 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
583 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
584 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
585 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
586 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
593 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
594 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
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/external/llvm-project/llvm/test/TableGen/
Dcond-let.td18 let n{8...6} = !cond(x{2}: 0b010, 1 : 0b110);
/external/exoplayer/tree/library/core/src/main/java/com/google/android/exoplayer2/
DRendererCapabilities.java71 int FORMAT_UNSUPPORTED_DRM = 0b010;
/external/mesa3d/src/intel/compiler/
Dbrw_reg_type.c206 GEN10_ALIGN1_3SRC_REG_TYPE_DF = 0b010,
213 GEN10_ALIGN1_3SRC_REG_TYPE_UW = 0b010,
/external/llvm-project/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td630 def RRA8r : II8r<0b010,
635 def RRA16r : II16r<0b010,
677 def RRA8m : II8m<0b010,
682 def RRA16m : II16m<0b010,
688 def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>;
689 def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>;
690 def RRA8p : II8p<0b010, (outs), (ins postreg:$rs), "rra.b\t$rs", []>;
691 def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td630 def RRA8r : II8r<0b010,
635 def RRA16r : II16r<0b010,
677 def RRA8m : II8m<0b010,
682 def RRA16m : II16m<0b010,
688 def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>;
689 def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>;
690 def RRA8p : II8p<0b010, (outs), (ins postreg:$rs), "rra.b\t$rs", []>;
691 def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>;
/external/skia/src/gpu/geometry/
DGrShape.h199 kIgnoreWinding_Flag = 0b010,

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