Searched refs:b1101 (Results 1 – 25 of 55) sorted by relevance
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127 def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>;136 def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>;145 def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;631 def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;638 def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;652 def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;694 def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>;695 def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>;696 def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>;697 def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;[all …]
205 defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv", int_aarch64_sve_fdiv>;325 defm ORNS_PPzPP : sve_int_pred_log<0b1101, "orns", null_frag>;355 defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;401 defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>;419 defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>;437 defm LDFF1SB_S : sve_mem_cldff_ss<0b1101, "ldff1sb", Z_s, ZPR32, GPR64shifted8>;1254 defm SQRDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1101, "sqrdmulh">;1297 defm SMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1101, "smlslt">;1382 defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;1639 defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep">;
132 def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>;141 def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>;150 def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;636 def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;643 def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;657 def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;699 def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>;700 def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>;701 def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>;702 def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;[all …]
421 …defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv", "FDIV_ZPZZ", int_aarch64_sve_fdiv, Destructive…653 defm ORNS_PPzPP : sve_int_pred_log<0b1101, "orns", null_frag>;695 defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;741 defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>;759 defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>;777 defm LDFF1SB_S : sve_mem_cldff_ss<0b1101, "ldff1sb", Z_s, ZPR32, GPR64shifted8>;2408 …defm SQRDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1101, "sqrdmulh", int_aarch64_sve_sqrdmulh_lan…2468 …defm SMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1101, "smlslt", int_aarch64_sve_smlslt_lane…2561 …defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr", "URSHR_ZPZI", int_aarch64_s…2823 defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep", int_aarch64_sve_bdep_x>;
379 def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;386 def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;400 def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;476 def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>;492 def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>;508 def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>;524 def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>;603 def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>;604 def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>;605 def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>;[all …]
100 let Inst{12-9} = 0b1101;342 let Inst{12-9} = 0b1101;416 let Inst{12-9} = 0b1101;554 let Inst{12-9} = 0b1101;616 let Inst{12-9} = 0b1101;
54 let Inst{27-24} = 0b1101;123 let IClass = 0b1101;
227 let IClass = 0b1101;228 let Inst{27-24} = 0b1101;778 let Inst{27-24} =0b1101;1286 let Inst{24-21} = 0b1101;1882 let IClass = 0b1101;1904 let IClass = 0b1101;1926 let IClass = 0b1101;1970 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;2109 let IClass = 0b1101;2127 let IClass = 0b1101;[all …]
249 let IClass = 0b1101;261 let IClass = 0b1101;897 let IClass = 0b1101;914 let IClass = 0b1101;
118 TEET = 0b1101,
279 defm : int_cond_alias<"cc", 0b1101>;291 defm : int_cond_alias<"geu", 0b1101>; // same as cc307 defm : fp_cond_alias<"le", 0b1101>;330 defm : cp_cond_alias<"01", 0b1101>;
278 defm : int_cond_alias<"cc", 0b1101>;290 defm : int_cond_alias<"geu", 0b1101>; // same as cc306 defm : fp_cond_alias<"le", 0b1101>;329 defm : cp_cond_alias<"01", 0b1101>;
144 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),149 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),159 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),166 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),171 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),181 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),1507 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1523 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1542 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,1603 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,[all …]
656 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.673 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.709 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.762 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.837 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1424 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1443 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1467 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),1502 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,1507 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.[all …]
154 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),169 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),189 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),204 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),1589 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1605 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1624 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,1685 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,[all …]
632 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.649 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.685 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.738 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.813 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1406 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1425 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1449 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),1484 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,1489 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.[all …]
699 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.716 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.752 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.793 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.856 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1411 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1430 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.1454 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),1482 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,1487 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.[all …]
101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),120 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),1390 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1405 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1423 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,1473 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,[all …]
428 let Inst{6-3} = 0b1101;614 let Inst{15-12} = 0b1101;1130 T1DataProcessing<0b1101> {1257 let Inst{15-12} = 0b1101;
2384 let Inst{19-16} = 0b1101; // SP2530 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,2536 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),2650 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;2652 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2665 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),2781 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;3250 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,3264 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,3275 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),[all …]
384 unsigned mask = coord_mode ? 0b1101 : 0b1001; in fd3_program_emit()
66 def LSWidth256 : RISCVWidth<0b1101>;
488 unsigned mask = coord_mode ? 0b1101 : 0b1001; in fd4_program_emit()
140 b1101 = 0xD, enumerator151 { true, false, false, b0010, b0010, b1101, false, NONE },