Searched refs:base_hi (Results 1 – 6 of 6) sorted by relevance
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | chain-hi-to-lo.ll | 37 …@chain_hi_to_lo_private_different_bases(half addrspace(5)* %base_lo, half addrspace(5)* %base_hi) {
57 %load_hi = load half, half addrspace(5)* %base_hi
115 …> @chain_hi_to_lo_group_different_bases(half addrspace(3)* %base_lo, half addrspace(3)* %base_hi) {
126 %load_hi = load half, half addrspace(3)* %base_hi
159 … @chain_hi_to_lo_global_different_bases(half addrspace(1)* %base_lo, half addrspace(1)* %base_hi) {
170 %load_hi = load half, half addrspace(1)* %base_hi
203 define <2 x half> @chain_hi_to_lo_flat_different_bases(half* %base_lo, half* %base_hi) {
214 %load_hi = load half, half* %base_hi
|
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | mtrr.h | 72 __u32 base_hi; member
|
| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_compiler_nir.c | 755 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1; in emit_intrinsic_load_ubo() local
767 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1); in emit_intrinsic_load_ubo()
770 base_hi = create_uniform_indirect(b, ubo + 1, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz)); in emit_intrinsic_load_ubo()
812 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0); in emit_intrinsic_load_ubo()
814 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2); in emit_intrinsic_load_ubo()
|
| D | instr-a3xx.h | 700 uint32_t base_hi : 2; member
|
| D | ir3.c | 485 cat5->s2en_bindless.base_hi = instr->cat5.tex_base >> 1; in emit_cat5()
|
| D | disasm-a3xx.c | 780 unsigned base = (cat5->s2en_bindless.base_hi << 1) | cat5->base_lo; in print_instr_cat5()
|