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/external/llvm-project/llvm/test/MC/Disassembler/RISCV/
Dbranch-targets.txt10 bnez a0, label1
11 bnez a0, label2
15 bnez a0, label1
16 bnez a0, label2
24 # CHECK-NEXT: c.bnez a0, 0x0 <label1>
25 # CHECK-NEXT: c.bnez a0, 0x18 <label2>
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dhalf-select-fcmp.ll26 ; RV32IZFH-NEXT: bnez a0, .LBB1_2
35 ; RV64IZFH-NEXT: bnez a0, .LBB1_2
49 ; RV32IZFH-NEXT: bnez a0, .LBB2_2
58 ; RV64IZFH-NEXT: bnez a0, .LBB2_2
72 ; RV32IZFH-NEXT: bnez a0, .LBB3_2
81 ; RV64IZFH-NEXT: bnez a0, .LBB3_2
95 ; RV32IZFH-NEXT: bnez a0, .LBB4_2
104 ; RV64IZFH-NEXT: bnez a0, .LBB4_2
118 ; RV32IZFH-NEXT: bnez a0, .LBB5_2
127 ; RV64IZFH-NEXT: bnez a0, .LBB5_2
[all …]
Dfloat-select-fcmp.ll28 ; RV32IF-NEXT: bnez a0, .LBB1_2
40 ; RV64IF-NEXT: bnez a0, .LBB1_2
57 ; RV32IF-NEXT: bnez a0, .LBB2_2
69 ; RV64IF-NEXT: bnez a0, .LBB2_2
86 ; RV32IF-NEXT: bnez a0, .LBB3_2
98 ; RV64IF-NEXT: bnez a0, .LBB3_2
115 ; RV32IF-NEXT: bnez a0, .LBB4_2
127 ; RV64IF-NEXT: bnez a0, .LBB4_2
144 ; RV32IF-NEXT: bnez a0, .LBB5_2
156 ; RV64IF-NEXT: bnez a0, .LBB5_2
[all …]
Dhalf-br-fcmp.ll17 ; RV32IZFH-NEXT: bnez a0, .LBB0_2
30 ; RV64IZFH-NEXT: bnez a0, .LBB0_2
52 ; RV32IZFH-NEXT: bnez a0, .LBB1_2
65 ; RV64IZFH-NEXT: bnez a0, .LBB1_2
127 ; RV32IZFH-NEXT: bnez a0, .LBB3_2
140 ; RV64IZFH-NEXT: bnez a0, .LBB3_2
162 ; RV32IZFH-NEXT: bnez a0, .LBB4_2
175 ; RV64IZFH-NEXT: bnez a0, .LBB4_2
197 ; RV32IZFH-NEXT: bnez a0, .LBB5_2
210 ; RV64IZFH-NEXT: bnez a0, .LBB5_2
[all …]
Ddouble-select-fcmp.ll34 ; RV32IFD-NEXT: bnez a0, .LBB1_2
49 ; RV64IFD-NEXT: bnez a0, .LBB1_2
71 ; RV32IFD-NEXT: bnez a0, .LBB2_2
86 ; RV64IFD-NEXT: bnez a0, .LBB2_2
108 ; RV32IFD-NEXT: bnez a0, .LBB3_2
123 ; RV64IFD-NEXT: bnez a0, .LBB3_2
145 ; RV32IFD-NEXT: bnez a0, .LBB4_2
160 ; RV64IFD-NEXT: bnez a0, .LBB4_2
182 ; RV32IFD-NEXT: bnez a0, .LBB5_2
197 ; RV64IFD-NEXT: bnez a0, .LBB5_2
[all …]
Dselect-const.ll96 ; RV32I-NEXT: bnez a1, .LBB3_2
106 ; RV32IF-NEXT: bnez a1, .LBB3_2
116 ; RV64I-NEXT: bnez a1, .LBB3_2
126 ; RV64IFD-NEXT: bnez a1, .LBB3_2
140 ; RV32I-NEXT: bnez a1, .LBB4_2
148 ; RV32IF-NEXT: bnez a0, .LBB4_2
164 ; RV64I-NEXT: bnez a1, .LBB4_2
172 ; RV64IFD-NEXT: bnez a0, .LBB4_2
Dfloat-br-fcmp.ll17 ; RV32IF-NEXT: bnez a0, .LBB0_2
30 ; RV64IF-NEXT: bnez a0, .LBB0_2
54 ; RV32IF-NEXT: bnez a0, .LBB1_2
69 ; RV64IF-NEXT: bnez a0, .LBB1_2
137 ; RV32IF-NEXT: bnez a0, .LBB3_2
152 ; RV64IF-NEXT: bnez a0, .LBB3_2
176 ; RV32IF-NEXT: bnez a0, .LBB4_2
191 ; RV64IF-NEXT: bnez a0, .LBB4_2
215 ; RV32IF-NEXT: bnez a0, .LBB5_2
230 ; RV64IF-NEXT: bnez a0, .LBB5_2
[all …]
Ddouble-br-fcmp.ll16 ; RV32IFD-NEXT: bnez a0, .LBB0_2
29 ; RV64IFD-NEXT: bnez a0, .LBB0_2
57 ; RV32IFD-NEXT: bnez a0, .LBB1_2
72 ; RV64IFD-NEXT: bnez a0, .LBB1_2
148 ; RV32IFD-NEXT: bnez a0, .LBB3_2
163 ; RV64IFD-NEXT: bnez a0, .LBB3_2
191 ; RV32IFD-NEXT: bnez a0, .LBB4_2
206 ; RV64IFD-NEXT: bnez a0, .LBB4_2
234 ; RV32IFD-NEXT: bnez a0, .LBB5_2
249 ; RV64IFD-NEXT: bnez a0, .LBB5_2
[all …]
Dselect-optimize-multiple.ll52 ; RV32I-NEXT: bnez a1, .LBB1_6
101 ; RV32I-NEXT: bnez a5, .LBB2_2
113 ; RV64I-NEXT: bnez a3, .LBB2_2
128 ; RV32I-NEXT: bnez a1, .LBB3_2
132 ; RV32I-NEXT: bnez a1, .LBB3_5
141 ; RV32I-NEXT: bnez a1, .LBB3_4
148 ; RV32I-NEXT: bnez a1, .LBB3_9
166 ; RV64I-NEXT: bnez a5, .LBB3_2
182 ; RV32I-NEXT: bnez a0, .LBB4_2
198 ; RV64I-NEXT: bnez a0, .LBB4_2
[all …]
/external/llvm-project/llvm/test/MC/RISCV/
Drv64-relaxation.s20 c.bnez a0, NEAR
21 #INSTR: c.bnez a0, 0x90e
22 #RELAX-INSTR: c.bnez a0, 0
24 c.bnez a0, NEAR_NEGATIVE
25 #INSTR: c.bnez a0, 0x8d4
26 #RELAX-INSTR: c.bnez a0, 0
28 c.bnez a0, FAR_BRANCH
32 c.bnez a0, FAR_BRANCH_NEGATIVE
36 c.bnez a0, FAR_JUMP
40 c.bnez a0, FAR_JUMP_NEGATIVE
Drv32-relaxation.s20 c.bnez a0, NEAR
21 #INSTR: c.bnez a0, 0x91e
22 #RELAX-INSTR: c.bnez a0, 0
24 c.bnez a0, NEAR_NEGATIVE
25 #INSTR: c.bnez a0, 0x8d4
26 #RELAX-INSTR: c.bnez a0, 0
28 c.bnez a0, FAR_BRANCH
32 c.bnez a0, FAR_BRANCH_NEGATIVE
36 c.bnez a0, FAR_JUMP
40 c.bnez a0, FAR_JUMP_NEGATIVE
Dcompressed-relocations.s18 c.bnez a0, foo
19 # A compressed branch (c.bnez) to an unresolved symbol will be relaxed to a (bnez).
21 # INSTR: c.bnez a0, foo
/external/llvm/test/MC/Mips/
Dmacro-divu.s7 # CHECK-NOTRAP: bnez $11, 8 # encoding: [0x15,0x60,0x00,0x02]
13 # CHECK-NOTRAP: bnez $12, 8 # encoding: [0x15,0x80,0x00,0x02]
19 # CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
31 # CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
37 # CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
43 # CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
Dbranch-pseudos.s9 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
14 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
32 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
37 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
43 # CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A]
149 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
154 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
172 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
177 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
181 # CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A]
[all …]
Dmacro-bcc-imm.s8 # ALL: bnez $1, foo
20 # ALL: bnez $1, foo
24 # ALL: bnez $1, foo
36 # ALL: bnez $1, foo
Ddouble-expand.s7 bnez $2, foo
10 # CHECK: bnez $2, foo
/external/llvm/test/CodeGen/Mips/
Dlcb2.ll10 define i32 @bnez() #0 {
24 ; lcb: .ent bnez
25 ; lcbn: .ent bnez
26 ; lcb: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}}
27 ; lcbn-NOT: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
28 ; lcb: .end bnez
29 ; lcbn: .end bnez
/external/llvm-project/llvm/test/CodeGen/Mips/
Dlcb2.ll10 define i32 @bnez() #0 {
24 ; lcb: .ent bnez
25 ; lcbn: .ent bnez
26 ; lcb: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}}
27 ; lcbn-NOT: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
28 ; lcb: .end bnez
29 ; lcbn: .end bnez
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-int.ll38 ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
39 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
74 ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
75 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
110 ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
111 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
147 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
152 ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
177 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
221 ; M2: bnez $[[T2]], [[BB0:\$BB[0-9_]+]]
[all …]
/external/llvm-project/llvm/test/MC/Mips/
Dbranch-pseudos.s9 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
14 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
32 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
37 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
43 # CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A]
149 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
154 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
172 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
177 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
181 # CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A]
[all …]
Ddouble-expand.s7 bnez $2, foo
10 # CHECK: bnez $2, foo
Dmicromips-el-fixup-data.s17 bnez $9, lab1
19 # CHECK: 09 b4 03 00 bnez $9, 10
/external/llvm-project/lld/test/ELF/
Driscv-branch.s11 # CHECK-32: e3 1e 00 fe bnez zero, 0x110b4
13 # CHECK-64: e3 1e 00 fe bnez zero, 0x11120
20 # LIMITS-32-NEXT: 63 10 00 80 bnez zero, 0x100b8
22 # LIMITS-64-NEXT: 63 10 00 80 bnez zero, 0x10124
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-int.ll38 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
73 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
108 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
143 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
148 ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
173 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
217 ; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
226 ; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dlong_ambiguous_chain_s32.ll23 ; MIPS32-NEXT: bnez $1, $BB0_12
31 ; MIPS32-NEXT: bnez $1, $BB0_7
39 ; MIPS32-NEXT: bnez $1, $BB0_8
66 ; MIPS32-NEXT: bnez $1, $BB0_11
81 ; MIPS32-NEXT: bnez $1, $BB0_14
102 ; MIPS32-NEXT: bnez $1, $BB0_19
210 ; MIPS32-NEXT: bnez $1, $BB1_12
218 ; MIPS32-NEXT: bnez $1, $BB1_7
226 ; MIPS32-NEXT: bnez $1, $BB1_8
255 ; MIPS32-NEXT: bnez $1, $BB1_11
[all …]

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