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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IFD %s
4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IFD %s
6
7declare void @abort()
8declare void @exit(i32)
9
10define void @br_fcmp_false(double %a, double %b) nounwind {
11; RV32IFD-LABEL: br_fcmp_false:
12; RV32IFD:       # %bb.0:
13; RV32IFD-NEXT:    addi sp, sp, -16
14; RV32IFD-NEXT:    sw ra, 12(sp)
15; RV32IFD-NEXT:    addi a0, zero, 1
16; RV32IFD-NEXT:    bnez a0, .LBB0_2
17; RV32IFD-NEXT:  # %bb.1: # %if.then
18; RV32IFD-NEXT:    lw ra, 12(sp)
19; RV32IFD-NEXT:    addi sp, sp, 16
20; RV32IFD-NEXT:    ret
21; RV32IFD-NEXT:  .LBB0_2: # %if.else
22; RV32IFD-NEXT:    call abort
23;
24; RV64IFD-LABEL: br_fcmp_false:
25; RV64IFD:       # %bb.0:
26; RV64IFD-NEXT:    addi sp, sp, -16
27; RV64IFD-NEXT:    sd ra, 8(sp)
28; RV64IFD-NEXT:    addi a0, zero, 1
29; RV64IFD-NEXT:    bnez a0, .LBB0_2
30; RV64IFD-NEXT:  # %bb.1: # %if.then
31; RV64IFD-NEXT:    ld ra, 8(sp)
32; RV64IFD-NEXT:    addi sp, sp, 16
33; RV64IFD-NEXT:    ret
34; RV64IFD-NEXT:  .LBB0_2: # %if.else
35; RV64IFD-NEXT:    call abort
36  %1 = fcmp false double %a, %b
37  br i1 %1, label %if.then, label %if.else
38if.then:
39  ret void
40if.else:
41  tail call void @abort()
42  unreachable
43}
44
45define void @br_fcmp_oeq(double %a, double %b) nounwind {
46; RV32IFD-LABEL: br_fcmp_oeq:
47; RV32IFD:       # %bb.0:
48; RV32IFD-NEXT:    addi sp, sp, -16
49; RV32IFD-NEXT:    sw ra, 12(sp)
50; RV32IFD-NEXT:    sw a2, 0(sp)
51; RV32IFD-NEXT:    sw a3, 4(sp)
52; RV32IFD-NEXT:    fld ft0, 0(sp)
53; RV32IFD-NEXT:    sw a0, 0(sp)
54; RV32IFD-NEXT:    sw a1, 4(sp)
55; RV32IFD-NEXT:    fld ft1, 0(sp)
56; RV32IFD-NEXT:    feq.d a0, ft1, ft0
57; RV32IFD-NEXT:    bnez a0, .LBB1_2
58; RV32IFD-NEXT:  # %bb.1: # %if.else
59; RV32IFD-NEXT:    lw ra, 12(sp)
60; RV32IFD-NEXT:    addi sp, sp, 16
61; RV32IFD-NEXT:    ret
62; RV32IFD-NEXT:  .LBB1_2: # %if.then
63; RV32IFD-NEXT:    call abort
64;
65; RV64IFD-LABEL: br_fcmp_oeq:
66; RV64IFD:       # %bb.0:
67; RV64IFD-NEXT:    addi sp, sp, -16
68; RV64IFD-NEXT:    sd ra, 8(sp)
69; RV64IFD-NEXT:    fmv.d.x ft0, a1
70; RV64IFD-NEXT:    fmv.d.x ft1, a0
71; RV64IFD-NEXT:    feq.d a0, ft1, ft0
72; RV64IFD-NEXT:    bnez a0, .LBB1_2
73; RV64IFD-NEXT:  # %bb.1: # %if.else
74; RV64IFD-NEXT:    ld ra, 8(sp)
75; RV64IFD-NEXT:    addi sp, sp, 16
76; RV64IFD-NEXT:    ret
77; RV64IFD-NEXT:  .LBB1_2: # %if.then
78; RV64IFD-NEXT:    call abort
79  %1 = fcmp oeq double %a, %b
80  br i1 %1, label %if.then, label %if.else
81if.else:
82  ret void
83if.then:
84  tail call void @abort()
85  unreachable
86}
87
88; TODO: generated code quality for this is very poor due to
89; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
90; expansion.
91define void @br_fcmp_oeq_alt(double %a, double %b) nounwind {
92; RV32IFD-LABEL: br_fcmp_oeq_alt:
93; RV32IFD:       # %bb.0:
94; RV32IFD-NEXT:    addi sp, sp, -16
95; RV32IFD-NEXT:    sw ra, 12(sp)
96; RV32IFD-NEXT:    sw a2, 0(sp)
97; RV32IFD-NEXT:    sw a3, 4(sp)
98; RV32IFD-NEXT:    fld ft0, 0(sp)
99; RV32IFD-NEXT:    sw a0, 0(sp)
100; RV32IFD-NEXT:    sw a1, 4(sp)
101; RV32IFD-NEXT:    fld ft1, 0(sp)
102; RV32IFD-NEXT:    feq.d a0, ft1, ft0
103; RV32IFD-NEXT:    xori a0, a0, 1
104; RV32IFD-NEXT:    beqz a0, .LBB2_2
105; RV32IFD-NEXT:  # %bb.1: # %if.else
106; RV32IFD-NEXT:    lw ra, 12(sp)
107; RV32IFD-NEXT:    addi sp, sp, 16
108; RV32IFD-NEXT:    ret
109; RV32IFD-NEXT:  .LBB2_2: # %if.then
110; RV32IFD-NEXT:    call abort
111;
112; RV64IFD-LABEL: br_fcmp_oeq_alt:
113; RV64IFD:       # %bb.0:
114; RV64IFD-NEXT:    addi sp, sp, -16
115; RV64IFD-NEXT:    sd ra, 8(sp)
116; RV64IFD-NEXT:    fmv.d.x ft0, a1
117; RV64IFD-NEXT:    fmv.d.x ft1, a0
118; RV64IFD-NEXT:    feq.d a0, ft1, ft0
119; RV64IFD-NEXT:    xori a0, a0, 1
120; RV64IFD-NEXT:    beqz a0, .LBB2_2
121; RV64IFD-NEXT:  # %bb.1: # %if.else
122; RV64IFD-NEXT:    ld ra, 8(sp)
123; RV64IFD-NEXT:    addi sp, sp, 16
124; RV64IFD-NEXT:    ret
125; RV64IFD-NEXT:  .LBB2_2: # %if.then
126; RV64IFD-NEXT:    call abort
127  %1 = fcmp oeq double %a, %b
128  br i1 %1, label %if.then, label %if.else
129if.then:
130  tail call void @abort()
131  unreachable
132if.else:
133  ret void
134}
135
136define void @br_fcmp_ogt(double %a, double %b) nounwind {
137; RV32IFD-LABEL: br_fcmp_ogt:
138; RV32IFD:       # %bb.0:
139; RV32IFD-NEXT:    addi sp, sp, -16
140; RV32IFD-NEXT:    sw ra, 12(sp)
141; RV32IFD-NEXT:    sw a0, 0(sp)
142; RV32IFD-NEXT:    sw a1, 4(sp)
143; RV32IFD-NEXT:    fld ft0, 0(sp)
144; RV32IFD-NEXT:    sw a2, 0(sp)
145; RV32IFD-NEXT:    sw a3, 4(sp)
146; RV32IFD-NEXT:    fld ft1, 0(sp)
147; RV32IFD-NEXT:    flt.d a0, ft1, ft0
148; RV32IFD-NEXT:    bnez a0, .LBB3_2
149; RV32IFD-NEXT:  # %bb.1: # %if.else
150; RV32IFD-NEXT:    lw ra, 12(sp)
151; RV32IFD-NEXT:    addi sp, sp, 16
152; RV32IFD-NEXT:    ret
153; RV32IFD-NEXT:  .LBB3_2: # %if.then
154; RV32IFD-NEXT:    call abort
155;
156; RV64IFD-LABEL: br_fcmp_ogt:
157; RV64IFD:       # %bb.0:
158; RV64IFD-NEXT:    addi sp, sp, -16
159; RV64IFD-NEXT:    sd ra, 8(sp)
160; RV64IFD-NEXT:    fmv.d.x ft0, a0
161; RV64IFD-NEXT:    fmv.d.x ft1, a1
162; RV64IFD-NEXT:    flt.d a0, ft1, ft0
163; RV64IFD-NEXT:    bnez a0, .LBB3_2
164; RV64IFD-NEXT:  # %bb.1: # %if.else
165; RV64IFD-NEXT:    ld ra, 8(sp)
166; RV64IFD-NEXT:    addi sp, sp, 16
167; RV64IFD-NEXT:    ret
168; RV64IFD-NEXT:  .LBB3_2: # %if.then
169; RV64IFD-NEXT:    call abort
170  %1 = fcmp ogt double %a, %b
171  br i1 %1, label %if.then, label %if.else
172if.else:
173  ret void
174if.then:
175  tail call void @abort()
176  unreachable
177}
178
179define void @br_fcmp_oge(double %a, double %b) nounwind {
180; RV32IFD-LABEL: br_fcmp_oge:
181; RV32IFD:       # %bb.0:
182; RV32IFD-NEXT:    addi sp, sp, -16
183; RV32IFD-NEXT:    sw ra, 12(sp)
184; RV32IFD-NEXT:    sw a0, 0(sp)
185; RV32IFD-NEXT:    sw a1, 4(sp)
186; RV32IFD-NEXT:    fld ft0, 0(sp)
187; RV32IFD-NEXT:    sw a2, 0(sp)
188; RV32IFD-NEXT:    sw a3, 4(sp)
189; RV32IFD-NEXT:    fld ft1, 0(sp)
190; RV32IFD-NEXT:    fle.d a0, ft1, ft0
191; RV32IFD-NEXT:    bnez a0, .LBB4_2
192; RV32IFD-NEXT:  # %bb.1: # %if.else
193; RV32IFD-NEXT:    lw ra, 12(sp)
194; RV32IFD-NEXT:    addi sp, sp, 16
195; RV32IFD-NEXT:    ret
196; RV32IFD-NEXT:  .LBB4_2: # %if.then
197; RV32IFD-NEXT:    call abort
198;
199; RV64IFD-LABEL: br_fcmp_oge:
200; RV64IFD:       # %bb.0:
201; RV64IFD-NEXT:    addi sp, sp, -16
202; RV64IFD-NEXT:    sd ra, 8(sp)
203; RV64IFD-NEXT:    fmv.d.x ft0, a0
204; RV64IFD-NEXT:    fmv.d.x ft1, a1
205; RV64IFD-NEXT:    fle.d a0, ft1, ft0
206; RV64IFD-NEXT:    bnez a0, .LBB4_2
207; RV64IFD-NEXT:  # %bb.1: # %if.else
208; RV64IFD-NEXT:    ld ra, 8(sp)
209; RV64IFD-NEXT:    addi sp, sp, 16
210; RV64IFD-NEXT:    ret
211; RV64IFD-NEXT:  .LBB4_2: # %if.then
212; RV64IFD-NEXT:    call abort
213  %1 = fcmp oge double %a, %b
214  br i1 %1, label %if.then, label %if.else
215if.else:
216  ret void
217if.then:
218  tail call void @abort()
219  unreachable
220}
221
222define void @br_fcmp_olt(double %a, double %b) nounwind {
223; RV32IFD-LABEL: br_fcmp_olt:
224; RV32IFD:       # %bb.0:
225; RV32IFD-NEXT:    addi sp, sp, -16
226; RV32IFD-NEXT:    sw ra, 12(sp)
227; RV32IFD-NEXT:    sw a2, 0(sp)
228; RV32IFD-NEXT:    sw a3, 4(sp)
229; RV32IFD-NEXT:    fld ft0, 0(sp)
230; RV32IFD-NEXT:    sw a0, 0(sp)
231; RV32IFD-NEXT:    sw a1, 4(sp)
232; RV32IFD-NEXT:    fld ft1, 0(sp)
233; RV32IFD-NEXT:    flt.d a0, ft1, ft0
234; RV32IFD-NEXT:    bnez a0, .LBB5_2
235; RV32IFD-NEXT:  # %bb.1: # %if.else
236; RV32IFD-NEXT:    lw ra, 12(sp)
237; RV32IFD-NEXT:    addi sp, sp, 16
238; RV32IFD-NEXT:    ret
239; RV32IFD-NEXT:  .LBB5_2: # %if.then
240; RV32IFD-NEXT:    call abort
241;
242; RV64IFD-LABEL: br_fcmp_olt:
243; RV64IFD:       # %bb.0:
244; RV64IFD-NEXT:    addi sp, sp, -16
245; RV64IFD-NEXT:    sd ra, 8(sp)
246; RV64IFD-NEXT:    fmv.d.x ft0, a1
247; RV64IFD-NEXT:    fmv.d.x ft1, a0
248; RV64IFD-NEXT:    flt.d a0, ft1, ft0
249; RV64IFD-NEXT:    bnez a0, .LBB5_2
250; RV64IFD-NEXT:  # %bb.1: # %if.else
251; RV64IFD-NEXT:    ld ra, 8(sp)
252; RV64IFD-NEXT:    addi sp, sp, 16
253; RV64IFD-NEXT:    ret
254; RV64IFD-NEXT:  .LBB5_2: # %if.then
255; RV64IFD-NEXT:    call abort
256  %1 = fcmp olt double %a, %b
257  br i1 %1, label %if.then, label %if.else
258if.else:
259  ret void
260if.then:
261  tail call void @abort()
262  unreachable
263}
264
265define void @br_fcmp_ole(double %a, double %b) nounwind {
266; RV32IFD-LABEL: br_fcmp_ole:
267; RV32IFD:       # %bb.0:
268; RV32IFD-NEXT:    addi sp, sp, -16
269; RV32IFD-NEXT:    sw ra, 12(sp)
270; RV32IFD-NEXT:    sw a2, 0(sp)
271; RV32IFD-NEXT:    sw a3, 4(sp)
272; RV32IFD-NEXT:    fld ft0, 0(sp)
273; RV32IFD-NEXT:    sw a0, 0(sp)
274; RV32IFD-NEXT:    sw a1, 4(sp)
275; RV32IFD-NEXT:    fld ft1, 0(sp)
276; RV32IFD-NEXT:    fle.d a0, ft1, ft0
277; RV32IFD-NEXT:    bnez a0, .LBB6_2
278; RV32IFD-NEXT:  # %bb.1: # %if.else
279; RV32IFD-NEXT:    lw ra, 12(sp)
280; RV32IFD-NEXT:    addi sp, sp, 16
281; RV32IFD-NEXT:    ret
282; RV32IFD-NEXT:  .LBB6_2: # %if.then
283; RV32IFD-NEXT:    call abort
284;
285; RV64IFD-LABEL: br_fcmp_ole:
286; RV64IFD:       # %bb.0:
287; RV64IFD-NEXT:    addi sp, sp, -16
288; RV64IFD-NEXT:    sd ra, 8(sp)
289; RV64IFD-NEXT:    fmv.d.x ft0, a1
290; RV64IFD-NEXT:    fmv.d.x ft1, a0
291; RV64IFD-NEXT:    fle.d a0, ft1, ft0
292; RV64IFD-NEXT:    bnez a0, .LBB6_2
293; RV64IFD-NEXT:  # %bb.1: # %if.else
294; RV64IFD-NEXT:    ld ra, 8(sp)
295; RV64IFD-NEXT:    addi sp, sp, 16
296; RV64IFD-NEXT:    ret
297; RV64IFD-NEXT:  .LBB6_2: # %if.then
298; RV64IFD-NEXT:    call abort
299  %1 = fcmp ole double %a, %b
300  br i1 %1, label %if.then, label %if.else
301if.else:
302  ret void
303if.then:
304  tail call void @abort()
305  unreachable
306}
307
308; TODO: feq.s+sltiu+bne -> feq.s+beq
309define void @br_fcmp_one(double %a, double %b) nounwind {
310; RV32IFD-LABEL: br_fcmp_one:
311; RV32IFD:       # %bb.0:
312; RV32IFD-NEXT:    addi sp, sp, -16
313; RV32IFD-NEXT:    sw ra, 12(sp)
314; RV32IFD-NEXT:    sw a0, 0(sp)
315; RV32IFD-NEXT:    sw a1, 4(sp)
316; RV32IFD-NEXT:    fld ft0, 0(sp)
317; RV32IFD-NEXT:    sw a2, 0(sp)
318; RV32IFD-NEXT:    sw a3, 4(sp)
319; RV32IFD-NEXT:    fld ft1, 0(sp)
320; RV32IFD-NEXT:    feq.d a0, ft1, ft1
321; RV32IFD-NEXT:    feq.d a1, ft0, ft0
322; RV32IFD-NEXT:    and a0, a1, a0
323; RV32IFD-NEXT:    feq.d a1, ft0, ft1
324; RV32IFD-NEXT:    not a1, a1
325; RV32IFD-NEXT:    and a0, a1, a0
326; RV32IFD-NEXT:    bnez a0, .LBB7_2
327; RV32IFD-NEXT:  # %bb.1: # %if.else
328; RV32IFD-NEXT:    lw ra, 12(sp)
329; RV32IFD-NEXT:    addi sp, sp, 16
330; RV32IFD-NEXT:    ret
331; RV32IFD-NEXT:  .LBB7_2: # %if.then
332; RV32IFD-NEXT:    call abort
333;
334; RV64IFD-LABEL: br_fcmp_one:
335; RV64IFD:       # %bb.0:
336; RV64IFD-NEXT:    addi sp, sp, -16
337; RV64IFD-NEXT:    sd ra, 8(sp)
338; RV64IFD-NEXT:    fmv.d.x ft0, a0
339; RV64IFD-NEXT:    fmv.d.x ft1, a1
340; RV64IFD-NEXT:    feq.d a0, ft1, ft1
341; RV64IFD-NEXT:    feq.d a1, ft0, ft0
342; RV64IFD-NEXT:    and a0, a1, a0
343; RV64IFD-NEXT:    feq.d a1, ft0, ft1
344; RV64IFD-NEXT:    not a1, a1
345; RV64IFD-NEXT:    and a0, a1, a0
346; RV64IFD-NEXT:    bnez a0, .LBB7_2
347; RV64IFD-NEXT:  # %bb.1: # %if.else
348; RV64IFD-NEXT:    ld ra, 8(sp)
349; RV64IFD-NEXT:    addi sp, sp, 16
350; RV64IFD-NEXT:    ret
351; RV64IFD-NEXT:  .LBB7_2: # %if.then
352; RV64IFD-NEXT:    call abort
353  %1 = fcmp one double %a, %b
354  br i1 %1, label %if.then, label %if.else
355if.else:
356  ret void
357if.then:
358  tail call void @abort()
359  unreachable
360}
361
362define void @br_fcmp_ord(double %a, double %b) nounwind {
363; RV32IFD-LABEL: br_fcmp_ord:
364; RV32IFD:       # %bb.0:
365; RV32IFD-NEXT:    addi sp, sp, -16
366; RV32IFD-NEXT:    sw ra, 12(sp)
367; RV32IFD-NEXT:    sw a0, 0(sp)
368; RV32IFD-NEXT:    sw a1, 4(sp)
369; RV32IFD-NEXT:    fld ft0, 0(sp)
370; RV32IFD-NEXT:    sw a2, 0(sp)
371; RV32IFD-NEXT:    sw a3, 4(sp)
372; RV32IFD-NEXT:    fld ft1, 0(sp)
373; RV32IFD-NEXT:    feq.d a0, ft1, ft1
374; RV32IFD-NEXT:    feq.d a1, ft0, ft0
375; RV32IFD-NEXT:    and a0, a1, a0
376; RV32IFD-NEXT:    bnez a0, .LBB8_2
377; RV32IFD-NEXT:  # %bb.1: # %if.else
378; RV32IFD-NEXT:    lw ra, 12(sp)
379; RV32IFD-NEXT:    addi sp, sp, 16
380; RV32IFD-NEXT:    ret
381; RV32IFD-NEXT:  .LBB8_2: # %if.then
382; RV32IFD-NEXT:    call abort
383;
384; RV64IFD-LABEL: br_fcmp_ord:
385; RV64IFD:       # %bb.0:
386; RV64IFD-NEXT:    addi sp, sp, -16
387; RV64IFD-NEXT:    sd ra, 8(sp)
388; RV64IFD-NEXT:    fmv.d.x ft0, a0
389; RV64IFD-NEXT:    fmv.d.x ft1, a1
390; RV64IFD-NEXT:    feq.d a0, ft1, ft1
391; RV64IFD-NEXT:    feq.d a1, ft0, ft0
392; RV64IFD-NEXT:    and a0, a1, a0
393; RV64IFD-NEXT:    bnez a0, .LBB8_2
394; RV64IFD-NEXT:  # %bb.1: # %if.else
395; RV64IFD-NEXT:    ld ra, 8(sp)
396; RV64IFD-NEXT:    addi sp, sp, 16
397; RV64IFD-NEXT:    ret
398; RV64IFD-NEXT:  .LBB8_2: # %if.then
399; RV64IFD-NEXT:    call abort
400  %1 = fcmp ord double %a, %b
401  br i1 %1, label %if.then, label %if.else
402if.else:
403  ret void
404if.then:
405  tail call void @abort()
406  unreachable
407}
408
409define void @br_fcmp_ueq(double %a, double %b) nounwind {
410; RV32IFD-LABEL: br_fcmp_ueq:
411; RV32IFD:       # %bb.0:
412; RV32IFD-NEXT:    addi sp, sp, -16
413; RV32IFD-NEXT:    sw ra, 12(sp)
414; RV32IFD-NEXT:    sw a2, 0(sp)
415; RV32IFD-NEXT:    sw a3, 4(sp)
416; RV32IFD-NEXT:    fld ft0, 0(sp)
417; RV32IFD-NEXT:    sw a0, 0(sp)
418; RV32IFD-NEXT:    sw a1, 4(sp)
419; RV32IFD-NEXT:    fld ft1, 0(sp)
420; RV32IFD-NEXT:    feq.d a0, ft1, ft0
421; RV32IFD-NEXT:    feq.d a1, ft0, ft0
422; RV32IFD-NEXT:    feq.d a2, ft1, ft1
423; RV32IFD-NEXT:    and a1, a2, a1
424; RV32IFD-NEXT:    seqz a1, a1
425; RV32IFD-NEXT:    or a0, a0, a1
426; RV32IFD-NEXT:    bnez a0, .LBB9_2
427; RV32IFD-NEXT:  # %bb.1: # %if.else
428; RV32IFD-NEXT:    lw ra, 12(sp)
429; RV32IFD-NEXT:    addi sp, sp, 16
430; RV32IFD-NEXT:    ret
431; RV32IFD-NEXT:  .LBB9_2: # %if.then
432; RV32IFD-NEXT:    call abort
433;
434; RV64IFD-LABEL: br_fcmp_ueq:
435; RV64IFD:       # %bb.0:
436; RV64IFD-NEXT:    addi sp, sp, -16
437; RV64IFD-NEXT:    sd ra, 8(sp)
438; RV64IFD-NEXT:    fmv.d.x ft0, a1
439; RV64IFD-NEXT:    fmv.d.x ft1, a0
440; RV64IFD-NEXT:    feq.d a0, ft1, ft0
441; RV64IFD-NEXT:    feq.d a1, ft0, ft0
442; RV64IFD-NEXT:    feq.d a2, ft1, ft1
443; RV64IFD-NEXT:    and a1, a2, a1
444; RV64IFD-NEXT:    seqz a1, a1
445; RV64IFD-NEXT:    or a0, a0, a1
446; RV64IFD-NEXT:    bnez a0, .LBB9_2
447; RV64IFD-NEXT:  # %bb.1: # %if.else
448; RV64IFD-NEXT:    ld ra, 8(sp)
449; RV64IFD-NEXT:    addi sp, sp, 16
450; RV64IFD-NEXT:    ret
451; RV64IFD-NEXT:  .LBB9_2: # %if.then
452; RV64IFD-NEXT:    call abort
453  %1 = fcmp ueq double %a, %b
454  br i1 %1, label %if.then, label %if.else
455if.else:
456  ret void
457if.then:
458  tail call void @abort()
459  unreachable
460}
461
462define void @br_fcmp_ugt(double %a, double %b) nounwind {
463; RV32IFD-LABEL: br_fcmp_ugt:
464; RV32IFD:       # %bb.0:
465; RV32IFD-NEXT:    addi sp, sp, -16
466; RV32IFD-NEXT:    sw ra, 12(sp)
467; RV32IFD-NEXT:    sw a2, 0(sp)
468; RV32IFD-NEXT:    sw a3, 4(sp)
469; RV32IFD-NEXT:    fld ft0, 0(sp)
470; RV32IFD-NEXT:    sw a0, 0(sp)
471; RV32IFD-NEXT:    sw a1, 4(sp)
472; RV32IFD-NEXT:    fld ft1, 0(sp)
473; RV32IFD-NEXT:    fle.d a0, ft1, ft0
474; RV32IFD-NEXT:    xori a0, a0, 1
475; RV32IFD-NEXT:    bnez a0, .LBB10_2
476; RV32IFD-NEXT:  # %bb.1: # %if.else
477; RV32IFD-NEXT:    lw ra, 12(sp)
478; RV32IFD-NEXT:    addi sp, sp, 16
479; RV32IFD-NEXT:    ret
480; RV32IFD-NEXT:  .LBB10_2: # %if.then
481; RV32IFD-NEXT:    call abort
482;
483; RV64IFD-LABEL: br_fcmp_ugt:
484; RV64IFD:       # %bb.0:
485; RV64IFD-NEXT:    addi sp, sp, -16
486; RV64IFD-NEXT:    sd ra, 8(sp)
487; RV64IFD-NEXT:    fmv.d.x ft0, a1
488; RV64IFD-NEXT:    fmv.d.x ft1, a0
489; RV64IFD-NEXT:    fle.d a0, ft1, ft0
490; RV64IFD-NEXT:    xori a0, a0, 1
491; RV64IFD-NEXT:    bnez a0, .LBB10_2
492; RV64IFD-NEXT:  # %bb.1: # %if.else
493; RV64IFD-NEXT:    ld ra, 8(sp)
494; RV64IFD-NEXT:    addi sp, sp, 16
495; RV64IFD-NEXT:    ret
496; RV64IFD-NEXT:  .LBB10_2: # %if.then
497; RV64IFD-NEXT:    call abort
498  %1 = fcmp ugt double %a, %b
499  br i1 %1, label %if.then, label %if.else
500if.else:
501  ret void
502if.then:
503  tail call void @abort()
504  unreachable
505}
506
507define void @br_fcmp_uge(double %a, double %b) nounwind {
508; RV32IFD-LABEL: br_fcmp_uge:
509; RV32IFD:       # %bb.0:
510; RV32IFD-NEXT:    addi sp, sp, -16
511; RV32IFD-NEXT:    sw ra, 12(sp)
512; RV32IFD-NEXT:    sw a2, 0(sp)
513; RV32IFD-NEXT:    sw a3, 4(sp)
514; RV32IFD-NEXT:    fld ft0, 0(sp)
515; RV32IFD-NEXT:    sw a0, 0(sp)
516; RV32IFD-NEXT:    sw a1, 4(sp)
517; RV32IFD-NEXT:    fld ft1, 0(sp)
518; RV32IFD-NEXT:    flt.d a0, ft1, ft0
519; RV32IFD-NEXT:    xori a0, a0, 1
520; RV32IFD-NEXT:    bnez a0, .LBB11_2
521; RV32IFD-NEXT:  # %bb.1: # %if.else
522; RV32IFD-NEXT:    lw ra, 12(sp)
523; RV32IFD-NEXT:    addi sp, sp, 16
524; RV32IFD-NEXT:    ret
525; RV32IFD-NEXT:  .LBB11_2: # %if.then
526; RV32IFD-NEXT:    call abort
527;
528; RV64IFD-LABEL: br_fcmp_uge:
529; RV64IFD:       # %bb.0:
530; RV64IFD-NEXT:    addi sp, sp, -16
531; RV64IFD-NEXT:    sd ra, 8(sp)
532; RV64IFD-NEXT:    fmv.d.x ft0, a1
533; RV64IFD-NEXT:    fmv.d.x ft1, a0
534; RV64IFD-NEXT:    flt.d a0, ft1, ft0
535; RV64IFD-NEXT:    xori a0, a0, 1
536; RV64IFD-NEXT:    bnez a0, .LBB11_2
537; RV64IFD-NEXT:  # %bb.1: # %if.else
538; RV64IFD-NEXT:    ld ra, 8(sp)
539; RV64IFD-NEXT:    addi sp, sp, 16
540; RV64IFD-NEXT:    ret
541; RV64IFD-NEXT:  .LBB11_2: # %if.then
542; RV64IFD-NEXT:    call abort
543  %1 = fcmp uge double %a, %b
544  br i1 %1, label %if.then, label %if.else
545if.else:
546  ret void
547if.then:
548  tail call void @abort()
549  unreachable
550}
551
552define void @br_fcmp_ult(double %a, double %b) nounwind {
553; RV32IFD-LABEL: br_fcmp_ult:
554; RV32IFD:       # %bb.0:
555; RV32IFD-NEXT:    addi sp, sp, -16
556; RV32IFD-NEXT:    sw ra, 12(sp)
557; RV32IFD-NEXT:    sw a0, 0(sp)
558; RV32IFD-NEXT:    sw a1, 4(sp)
559; RV32IFD-NEXT:    fld ft0, 0(sp)
560; RV32IFD-NEXT:    sw a2, 0(sp)
561; RV32IFD-NEXT:    sw a3, 4(sp)
562; RV32IFD-NEXT:    fld ft1, 0(sp)
563; RV32IFD-NEXT:    fle.d a0, ft1, ft0
564; RV32IFD-NEXT:    xori a0, a0, 1
565; RV32IFD-NEXT:    bnez a0, .LBB12_2
566; RV32IFD-NEXT:  # %bb.1: # %if.else
567; RV32IFD-NEXT:    lw ra, 12(sp)
568; RV32IFD-NEXT:    addi sp, sp, 16
569; RV32IFD-NEXT:    ret
570; RV32IFD-NEXT:  .LBB12_2: # %if.then
571; RV32IFD-NEXT:    call abort
572;
573; RV64IFD-LABEL: br_fcmp_ult:
574; RV64IFD:       # %bb.0:
575; RV64IFD-NEXT:    addi sp, sp, -16
576; RV64IFD-NEXT:    sd ra, 8(sp)
577; RV64IFD-NEXT:    fmv.d.x ft0, a0
578; RV64IFD-NEXT:    fmv.d.x ft1, a1
579; RV64IFD-NEXT:    fle.d a0, ft1, ft0
580; RV64IFD-NEXT:    xori a0, a0, 1
581; RV64IFD-NEXT:    bnez a0, .LBB12_2
582; RV64IFD-NEXT:  # %bb.1: # %if.else
583; RV64IFD-NEXT:    ld ra, 8(sp)
584; RV64IFD-NEXT:    addi sp, sp, 16
585; RV64IFD-NEXT:    ret
586; RV64IFD-NEXT:  .LBB12_2: # %if.then
587; RV64IFD-NEXT:    call abort
588  %1 = fcmp ult double %a, %b
589  br i1 %1, label %if.then, label %if.else
590if.else:
591  ret void
592if.then:
593  tail call void @abort()
594  unreachable
595}
596
597define void @br_fcmp_ule(double %a, double %b) nounwind {
598; RV32IFD-LABEL: br_fcmp_ule:
599; RV32IFD:       # %bb.0:
600; RV32IFD-NEXT:    addi sp, sp, -16
601; RV32IFD-NEXT:    sw ra, 12(sp)
602; RV32IFD-NEXT:    sw a0, 0(sp)
603; RV32IFD-NEXT:    sw a1, 4(sp)
604; RV32IFD-NEXT:    fld ft0, 0(sp)
605; RV32IFD-NEXT:    sw a2, 0(sp)
606; RV32IFD-NEXT:    sw a3, 4(sp)
607; RV32IFD-NEXT:    fld ft1, 0(sp)
608; RV32IFD-NEXT:    flt.d a0, ft1, ft0
609; RV32IFD-NEXT:    xori a0, a0, 1
610; RV32IFD-NEXT:    bnez a0, .LBB13_2
611; RV32IFD-NEXT:  # %bb.1: # %if.else
612; RV32IFD-NEXT:    lw ra, 12(sp)
613; RV32IFD-NEXT:    addi sp, sp, 16
614; RV32IFD-NEXT:    ret
615; RV32IFD-NEXT:  .LBB13_2: # %if.then
616; RV32IFD-NEXT:    call abort
617;
618; RV64IFD-LABEL: br_fcmp_ule:
619; RV64IFD:       # %bb.0:
620; RV64IFD-NEXT:    addi sp, sp, -16
621; RV64IFD-NEXT:    sd ra, 8(sp)
622; RV64IFD-NEXT:    fmv.d.x ft0, a0
623; RV64IFD-NEXT:    fmv.d.x ft1, a1
624; RV64IFD-NEXT:    flt.d a0, ft1, ft0
625; RV64IFD-NEXT:    xori a0, a0, 1
626; RV64IFD-NEXT:    bnez a0, .LBB13_2
627; RV64IFD-NEXT:  # %bb.1: # %if.else
628; RV64IFD-NEXT:    ld ra, 8(sp)
629; RV64IFD-NEXT:    addi sp, sp, 16
630; RV64IFD-NEXT:    ret
631; RV64IFD-NEXT:  .LBB13_2: # %if.then
632; RV64IFD-NEXT:    call abort
633  %1 = fcmp ule double %a, %b
634  br i1 %1, label %if.then, label %if.else
635if.else:
636  ret void
637if.then:
638  tail call void @abort()
639  unreachable
640}
641
642define void @br_fcmp_une(double %a, double %b) nounwind {
643; RV32IFD-LABEL: br_fcmp_une:
644; RV32IFD:       # %bb.0:
645; RV32IFD-NEXT:    addi sp, sp, -16
646; RV32IFD-NEXT:    sw ra, 12(sp)
647; RV32IFD-NEXT:    sw a2, 0(sp)
648; RV32IFD-NEXT:    sw a3, 4(sp)
649; RV32IFD-NEXT:    fld ft0, 0(sp)
650; RV32IFD-NEXT:    sw a0, 0(sp)
651; RV32IFD-NEXT:    sw a1, 4(sp)
652; RV32IFD-NEXT:    fld ft1, 0(sp)
653; RV32IFD-NEXT:    feq.d a0, ft1, ft0
654; RV32IFD-NEXT:    xori a0, a0, 1
655; RV32IFD-NEXT:    bnez a0, .LBB14_2
656; RV32IFD-NEXT:  # %bb.1: # %if.else
657; RV32IFD-NEXT:    lw ra, 12(sp)
658; RV32IFD-NEXT:    addi sp, sp, 16
659; RV32IFD-NEXT:    ret
660; RV32IFD-NEXT:  .LBB14_2: # %if.then
661; RV32IFD-NEXT:    call abort
662;
663; RV64IFD-LABEL: br_fcmp_une:
664; RV64IFD:       # %bb.0:
665; RV64IFD-NEXT:    addi sp, sp, -16
666; RV64IFD-NEXT:    sd ra, 8(sp)
667; RV64IFD-NEXT:    fmv.d.x ft0, a1
668; RV64IFD-NEXT:    fmv.d.x ft1, a0
669; RV64IFD-NEXT:    feq.d a0, ft1, ft0
670; RV64IFD-NEXT:    xori a0, a0, 1
671; RV64IFD-NEXT:    bnez a0, .LBB14_2
672; RV64IFD-NEXT:  # %bb.1: # %if.else
673; RV64IFD-NEXT:    ld ra, 8(sp)
674; RV64IFD-NEXT:    addi sp, sp, 16
675; RV64IFD-NEXT:    ret
676; RV64IFD-NEXT:  .LBB14_2: # %if.then
677; RV64IFD-NEXT:    call abort
678  %1 = fcmp une double %a, %b
679  br i1 %1, label %if.then, label %if.else
680if.else:
681  ret void
682if.then:
683  tail call void @abort()
684  unreachable
685}
686
687define void @br_fcmp_uno(double %a, double %b) nounwind {
688; TODO: sltiu+bne -> beq
689; RV32IFD-LABEL: br_fcmp_uno:
690; RV32IFD:       # %bb.0:
691; RV32IFD-NEXT:    addi sp, sp, -16
692; RV32IFD-NEXT:    sw ra, 12(sp)
693; RV32IFD-NEXT:    sw a0, 0(sp)
694; RV32IFD-NEXT:    sw a1, 4(sp)
695; RV32IFD-NEXT:    fld ft0, 0(sp)
696; RV32IFD-NEXT:    sw a2, 0(sp)
697; RV32IFD-NEXT:    sw a3, 4(sp)
698; RV32IFD-NEXT:    fld ft1, 0(sp)
699; RV32IFD-NEXT:    feq.d a0, ft1, ft1
700; RV32IFD-NEXT:    feq.d a1, ft0, ft0
701; RV32IFD-NEXT:    and a0, a1, a0
702; RV32IFD-NEXT:    seqz a0, a0
703; RV32IFD-NEXT:    bnez a0, .LBB15_2
704; RV32IFD-NEXT:  # %bb.1: # %if.else
705; RV32IFD-NEXT:    lw ra, 12(sp)
706; RV32IFD-NEXT:    addi sp, sp, 16
707; RV32IFD-NEXT:    ret
708; RV32IFD-NEXT:  .LBB15_2: # %if.then
709; RV32IFD-NEXT:    call abort
710;
711; RV64IFD-LABEL: br_fcmp_uno:
712; RV64IFD:       # %bb.0:
713; RV64IFD-NEXT:    addi sp, sp, -16
714; RV64IFD-NEXT:    sd ra, 8(sp)
715; RV64IFD-NEXT:    fmv.d.x ft0, a0
716; RV64IFD-NEXT:    fmv.d.x ft1, a1
717; RV64IFD-NEXT:    feq.d a0, ft1, ft1
718; RV64IFD-NEXT:    feq.d a1, ft0, ft0
719; RV64IFD-NEXT:    and a0, a1, a0
720; RV64IFD-NEXT:    seqz a0, a0
721; RV64IFD-NEXT:    bnez a0, .LBB15_2
722; RV64IFD-NEXT:  # %bb.1: # %if.else
723; RV64IFD-NEXT:    ld ra, 8(sp)
724; RV64IFD-NEXT:    addi sp, sp, 16
725; RV64IFD-NEXT:    ret
726; RV64IFD-NEXT:  .LBB15_2: # %if.then
727; RV64IFD-NEXT:    call abort
728  %1 = fcmp uno double %a, %b
729  br i1 %1, label %if.then, label %if.else
730if.else:
731  ret void
732if.then:
733  tail call void @abort()
734  unreachable
735}
736
737define void @br_fcmp_true(double %a, double %b) nounwind {
738; RV32IFD-LABEL: br_fcmp_true:
739; RV32IFD:       # %bb.0:
740; RV32IFD-NEXT:    addi sp, sp, -16
741; RV32IFD-NEXT:    sw ra, 12(sp)
742; RV32IFD-NEXT:    addi a0, zero, 1
743; RV32IFD-NEXT:    bnez a0, .LBB16_2
744; RV32IFD-NEXT:  # %bb.1: # %if.else
745; RV32IFD-NEXT:    lw ra, 12(sp)
746; RV32IFD-NEXT:    addi sp, sp, 16
747; RV32IFD-NEXT:    ret
748; RV32IFD-NEXT:  .LBB16_2: # %if.then
749; RV32IFD-NEXT:    call abort
750;
751; RV64IFD-LABEL: br_fcmp_true:
752; RV64IFD:       # %bb.0:
753; RV64IFD-NEXT:    addi sp, sp, -16
754; RV64IFD-NEXT:    sd ra, 8(sp)
755; RV64IFD-NEXT:    addi a0, zero, 1
756; RV64IFD-NEXT:    bnez a0, .LBB16_2
757; RV64IFD-NEXT:  # %bb.1: # %if.else
758; RV64IFD-NEXT:    ld ra, 8(sp)
759; RV64IFD-NEXT:    addi sp, sp, 16
760; RV64IFD-NEXT:    ret
761; RV64IFD-NEXT:  .LBB16_2: # %if.then
762; RV64IFD-NEXT:    call abort
763  %1 = fcmp true double %a, %b
764  br i1 %1, label %if.then, label %if.else
765if.else:
766  ret void
767if.then:
768  tail call void @abort()
769  unreachable
770}
771