Searched refs:brw_vec4_grf (Results 1 – 14 of 14) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_clip_tri.c | 55 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
67 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
86 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_tri_alloc_regs()
108 c->reg.dir = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
109 c->reg.offset = brw_vec4_grf(i, 4); in brw_clip_tri_alloc_regs()
111 c->reg.tmp0 = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
112 c->reg.tmp1 = brw_vec4_grf(i, 4); in brw_clip_tri_alloc_regs()
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| D | brw_clip_line.c | 48 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
60 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
68 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_line_alloc_regs()
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| D | brw_vec4_gs_nir.cpp | 89 emit(MOV(dest, retype(brw_vec4_grf(1, 0), BRW_REGISTER_TYPE_D))); in nir_emit_intrinsic()
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| D | brw_vec4_tes.cpp | 67 struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2)); in setup_payload()
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| D | brw_reg.h | 786 brw_vec4_grf(unsigned nr, unsigned subnr) in brw_vec4_grf() function
1143 struct brw_reg reg = brw_vec4_grf(0, 0); in brw_vec4_indirect()
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| D | brw_clip_util.c | 42 struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0); in get_tmp()
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| D | brw_vec4_gs_visitor.cpp | 167 dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD)); in emit_prolog()
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| D | brw_compile_sf.c | 103 return brw_vec4_grf(vert.nr + off, sub * 4); in get_vue_slot()
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| D | brw_vec4_generator.cpp | 719 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1)); in generate_gs_ff_sync()
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| D | brw_vec4.cpp | 2042 reg = stride(byte_offset(brw_vec4_grf( in convert_to_hw_regs()
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| D | brw_fs.cpp | 3382 mov->src[0] = brw_vec4_grf(mov->src[0].nr, 0); in emit_repclear_shader()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_ff_gs_emit.c | 70 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_ff_gs_alloc_regs()
79 retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
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| /external/igt-gpu-tools/assembler/ |
| D | brw_reg.h | 486 brw_vec4_grf(unsigned nr, unsigned subnr) in brw_vec4_grf() function
719 struct brw_reg reg = brw_vec4_grf(0, 0); in brw_vec4_indirect()
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| D | brw_eu_emit.c | 1088 brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); in brw_NOP()
1089 brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); in brw_NOP()
1457 brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); in brw_ENDIF()
1458 brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); in brw_ENDIF()
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