Searched refs:buffer_load (Results 1 – 25 of 25) sorted by relevance
/external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
D | ipra.ll | 22 ; GCN-NOT: buffer_load 28 ; GCN-NOT: buffer_load 44 ; GCN-NOT: buffer_load 50 ; GCN-NOT: buffer_load
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D | extract_vector_elt-i64.ll | 33 ; GCN-NOT: buffer_load 46 ; GCN-NOT: buffer_load 60 ; GCN-NOT: buffer_load 75 ; GCN-NOT: buffer_load
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D | extract_vector_elt-f64.ll | 16 ; GCN-NOT: buffer_load 31 ; GCN-NOT: buffer_load
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D | llvm.amdgcn.softwqm.ll | 112 ;CHECK: buffer_load 113 ;CHECK: buffer_load 148 ;CHECK: buffer_load 149 ;CHECK: buffer_load
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D | llvm.amdgcn.raw.buffer.load.format.ll | 4 ;CHECK-LABEL: {{^}}buffer_load: 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | wait.ll | 44 ; ILPMAX: buffer_load 47 ; ILPMAX: buffer_load
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D | llvm.amdgcn.struct.buffer.load.format.ll | 4 ;CHECK-LABEL: {{^}}buffer_load: 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | llvm.amdgcn.buffer.load.format.ll | 4 ;CHECK-LABEL: {{^}}buffer_load: 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | llvm.amdgcn.struct.buffer.load.ll | 4 ;CHECK-LABEL: {{^}}buffer_load: 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | no-shrink-extloads.ll | 7 ; using a buffer_load instruction.
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D | llvm.amdgcn.buffer.load.ll | 4 ;CHECK-LABEL: {{^}}buffer_load: 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | llvm.memcpy.ll | 350 ; SI-NOT: buffer_load
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D | llvm.amdgcn.raw.buffer.load.ll | 5 ;CHECK-LABEL: {{^}}buffer_load: 10 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | min.ll | 137 ; SI-NOT: buffer_load
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D | llvm.amdgcn.exp.ll | 619 ; GCN: buffer_load
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/external/llvm/test/CodeGen/AMDGPU/ |
D | wait.ll | 40 ; ILPMAX: buffer_load 43 ; ILPMAX: buffer_load
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D | llvm.amdgcn.buffer.load.ll | 4 ;CHECK-LABEL: {{^}}buffer_load: 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | llvm.amdgcn.buffer.load.format.ll | 4 ;CHECK-LABEL: {{^}}buffer_load: 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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D | no-shrink-extloads.ll | 7 ; using a buffer_load instruction.
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D | half.ll | 31 ; GCN-NOT: buffer_load 84 ; GCN-NOT: buffer_load
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_shader_llvm_tess.c | 268 static LLVMValueRef buffer_load(struct si_shader_context *ctx, LLVMTypeRef type, unsigned swizzle, in buffer_load() function 458 value[i] = buffer_load(ctx, type, i, ctx->tess_offchip_ring, base, addr, true); in si_nir_load_input_tes() 579 return buffer_load(ctx, ctx->ac.f32, ~0, ctx->tess_offchip_ring, base, addr, true); in load_tess_level()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | BUFInstructions.td | 1172 // buffer_load/store_format patterns
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | BUFInstructions.td | 1167 // buffer_load/store_format patterns
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstructions.td | 2150 // buffer_load/store_format patterns
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/external/llvm-project/llvm/docs/ |
D | AMDGPUUsage.rst | 4585 Private address space uses ``buffer_load/store`` using the scratch V#
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