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/external/mesa3d/src/gallium/frontends/clover/llvm/
Dcompat.hpp79 create_compiler_invocation_from_args(clang::CompilerInvocation &cinv, in create_compiler_invocation_from_args() argument
85 cinv, copts, diag); in create_compiler_invocation_from_args()
88 cinv, copts.data(), copts.data() + copts.size(), diag); in create_compiler_invocation_from_args()
/external/llvm-project/llvm/test/MC/ARM/
Dthumbv8.1m.s1075 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1076 # CHECK-FP: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1077 # CHECK-NOLOB: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1078 cinv lr, r12, hs label
1110 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
1111 # CHECK-FP: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
1112 # CHECK-NOLOB: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
Dmve-scalar-shift.s58 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
59 # CHECK-NOMVE: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
60 cinv lr, r12, hs label
86 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
87 # CHECK-NOMVE: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dthumbv8.1m.s11 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
32 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
Dthumb2-v8.1m.txt1124 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1145 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dcsel.ll47 ; CHECK-NEXT: cinv r0, r1, gt
60 ; CHECK-NEXT: cinv r0, r1, le
152 %cinv = xor i32 %c, -1
153 %spec.select = select i1 %cmp, i32 %b, i32 %cinv
330 ; CHECK-NEXT: cinv r0, r0, gt
Dmve-saturating-arith.ll62 ; CHECK-NEXT: cinv r0, r12, eq
92 ; CHECK-NEXT: cinv r1, r12, eq
228 ; CHECK-NEXT: cinv r0, r12, eq
258 ; CHECK-NEXT: cinv r1, r12, eq
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dssub_sat.ll17 ; CHECK-NEXT: cinv w8, w9, ge
31 ; CHECK-NEXT: cinv x8, x9, ge
Dsadd_sat_plus.ll17 ; CHECK-NEXT: cinv w9, w9, ge
32 ; CHECK-NEXT: cinv x8, x9, ge
Dsadd_sat.ll17 ; CHECK-NEXT: cinv w8, w9, ge
31 ; CHECK-NEXT: cinv x8, x9, ge
Dssub_sat_plus.ll17 ; CHECK-NEXT: cinv w9, w9, ge
32 ; CHECK-NEXT: cinv x8, x9, ge
Darm64-csel.ll28 ; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
117 ; CHECK: cinv w0, w[[REG]], eq
128 ; CHECK: cinv x0, x[[REG]], eq
Dssub_sat_vec.ll391 ; CHECK-NEXT: cinv x14, x8, ge
411 ; CHECK-NEXT: cinv x8, x8, ge
Dsadd_sat_vec.ll390 ; CHECK-NEXT: cinv x14, x8, ge
410 ; CHECK-NEXT: cinv x8, x8, ge
Dselect_const.ll340 ; CHECK-NEXT: cinv w0, w8, eq
/external/llvm/test/CodeGen/AArch64/
Darm64-csel.ll28 ; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
116 ; CHECK: cinv w0, w[[REG]], eq
127 ; CHECK: cinv x0, x[[REG]], eq
/external/llvm-project/llvm/test/MC/AArch64/
Dbasic-a64-diagnostics.s1428 cinv w3, wsp, ne
1429 cinv sp, x9, eq
1430 cinv w8, x7, nv
Dbasic-a64-instructions.s1425 cinv w3, w5, gt
1426 cinv wzr, w4, le
1427 cinv w9, wzr, lt
1432 cinv x3, x5, gt
1433 cinv xzr, x4, le
1434 cinv x9, xzr, lt
/external/llvm/test/MC/AArch64/
Dbasic-a64-diagnostics.s1414 cinv w3, wsp, ne
1415 cinv sp, x9, eq
1416 cinv w8, x7, nv
Dbasic-a64-instructions.s1425 cinv w3, w5, gt
1426 cinv wzr, w4, le
1427 cinv w9, wzr, lt
1432 cinv x3, x5, gt
1433 cinv xzr, x4, le
1434 cinv x9, xzr, lt
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s428 cinv w3, w5, gt label
429 cinv wzr, w4, le label
431 cinv x3, x5, gt label
432 cinv xzr, x4, le label
1760 # CHECK-NEXT: 1 3 0.50 cinv w3, w5, gt
1761 # CHECK-NEXT: 1 3 0.50 cinv wzr, w4, le
1763 # CHECK-NEXT: 1 3 0.50 cinv x3, x5, gt
1764 # CHECK-NEXT: 1 3 0.50 cinv xzr, x4, le
2943 …0.50 0.50 - - - - - - - - - - cinv w3, w5, gt
2944 ….50 0.50 - - - - - - - - - - cinv wzr, w4, le
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt977 # CHECK: cinv w3, w5, gt
978 # CHECK: cinv wzr, w4, le
980 # CHECK: cinv x3, x5, gt
981 # CHECK: cinv xzr, x4, le
983 # "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt981 # CHECK: cinv w3, w5, gt
982 # CHECK: cinv wzr, w4, le
984 # CHECK: cinv x3, x5, gt
985 # CHECK: cinv xzr, x4, le
987 # "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc95 __ cinv(w21, w22, eq); in GenerateTestSequenceBase() local
96 __ cinv(w21, w22, ne); in GenerateTestSequenceBase() local
97 __ cinv(x23, x24, cc); in GenerateTestSequenceBase() local
98 __ cinv(x23, x24, cs); in GenerateTestSequenceBase() local
Dtest-disasm-aarch64.cc2177 COMPARE(cinv(w1, w2, eq), "cinv w1, w2, eq"); in TEST()
2178 COMPARE(cinv(x3, x4, ne), "cinv x3, x4, ne"); in TEST()

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