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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
3
4declare i4 @llvm.sadd.sat.i4(i4, i4)
5declare i8 @llvm.sadd.sat.i8(i8, i8)
6declare i16 @llvm.sadd.sat.i16(i16, i16)
7declare i32 @llvm.sadd.sat.i32(i32, i32)
8declare i64 @llvm.sadd.sat.i64(i64, i64)
9declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
10
11define i32 @func(i32 %x, i32 %y) nounwind {
12; CHECK-LABEL: func:
13; CHECK:       // %bb.0:
14; CHECK-NEXT:    adds w8, w0, w1
15; CHECK-NEXT:    mov w9, #2147483647
16; CHECK-NEXT:    cmp w8, #0 // =0
17; CHECK-NEXT:    cinv w8, w9, ge
18; CHECK-NEXT:    adds w9, w0, w1
19; CHECK-NEXT:    csel w0, w8, w9, vs
20; CHECK-NEXT:    ret
21  %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
22  ret i32 %tmp;
23}
24
25define i64 @func2(i64 %x, i64 %y) nounwind {
26; CHECK-LABEL: func2:
27; CHECK:       // %bb.0:
28; CHECK-NEXT:    adds x8, x0, x1
29; CHECK-NEXT:    mov x9, #9223372036854775807
30; CHECK-NEXT:    cmp x8, #0 // =0
31; CHECK-NEXT:    cinv x8, x9, ge
32; CHECK-NEXT:    adds x9, x0, x1
33; CHECK-NEXT:    csel x0, x8, x9, vs
34; CHECK-NEXT:    ret
35  %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
36  ret i64 %tmp;
37}
38
39define i16 @func16(i16 %x, i16 %y) nounwind {
40; CHECK-LABEL: func16:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    sxth w8, w0
43; CHECK-NEXT:    mov w9, #32767
44; CHECK-NEXT:    add w8, w8, w1, sxth
45; CHECK-NEXT:    cmp w8, w9
46; CHECK-NEXT:    csel w8, w8, w9, lt
47; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
48; CHECK-NEXT:    mov w9, #-32768
49; CHECK-NEXT:    csel w0, w8, w9, gt
50; CHECK-NEXT:    ret
51  %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
52  ret i16 %tmp;
53}
54
55define i8 @func8(i8 %x, i8 %y) nounwind {
56; CHECK-LABEL: func8:
57; CHECK:       // %bb.0:
58; CHECK-NEXT:    sxtb w8, w0
59; CHECK-NEXT:    add w8, w8, w1, sxtb
60; CHECK-NEXT:    mov w9, #127
61; CHECK-NEXT:    cmp w8, #127 // =127
62; CHECK-NEXT:    csel w8, w8, w9, lt
63; CHECK-NEXT:    cmn w8, #128 // =128
64; CHECK-NEXT:    mov w9, #-128
65; CHECK-NEXT:    csel w0, w8, w9, gt
66; CHECK-NEXT:    ret
67  %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
68  ret i8 %tmp;
69}
70
71define i4 @func3(i4 %x, i4 %y) nounwind {
72; CHECK-LABEL: func3:
73; CHECK:       // %bb.0:
74; CHECK-NEXT:    lsl w8, w1, #28
75; CHECK-NEXT:    sbfx w9, w0, #0, #4
76; CHECK-NEXT:    add w8, w9, w8, asr #28
77; CHECK-NEXT:    mov w10, #7
78; CHECK-NEXT:    cmp w8, #7 // =7
79; CHECK-NEXT:    csel w8, w8, w10, lt
80; CHECK-NEXT:    cmn w8, #8 // =8
81; CHECK-NEXT:    mov w9, #-8
82; CHECK-NEXT:    csel w0, w8, w9, gt
83; CHECK-NEXT:    ret
84  %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
85  ret i4 %tmp;
86}
87
88define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
89; CHECK-LABEL: vec:
90; CHECK:       // %bb.0:
91; CHECK-NEXT:    sqadd v0.4s, v0.4s, v1.4s
92; CHECK-NEXT:    ret
93  %tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
94  ret <4 x i32> %tmp;
95}
96