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Searched refs:cntd (Results 1 – 17 of 17) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dcntd-diagnostics.s6 cntd w0 label
11 cntd sp label
16 cntd z0.b label
25 cntd x0, all, mul #-1 label
30 cntd x0, all, mul #0 label
35 cntd x0, all, mul #17 label
44 cntd x0, #-1 label
49 cntd x0, #32 label
54 cntd x0, vl512 label
Dcntd.s10 cntd x0 label
16 cntd x0, all label
22 cntd x0, all, mul #1 label
28 cntd x0, all, mul #16 label
34 cntd x0, pow2 label
40 cntd x0, #28 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-counting-elems.ll101 define i64 @cntd() {
102 ; CHECK-LABEL: cntd:
103 ; CHECK: cntd x0, vl5
105 %out = call i64 @llvm.aarch64.sve.cntd(i32 5)
111 ; CHECK: cntd x0, vl16, mul #15
113 %cnt = call i64 @llvm.aarch64.sve.cntd(i32 9)
120 ; CHECK: cntd x0, vl32, mul #16
122 %cnt = call i64 @llvm.aarch64.sve.cntd(i32 10)
170 declare i64 @llvm.aarch64.sve.cntd(i32 %pattern)
Dsve-vscale.ll173 ; CHECK-LABEL: cntd:
174 ; CHECK: cntd x0{{$}}
176 define i32 @cntd() nounwind {
183 ; CHECK: cntd x0, all, mul #15
192 ; CHECK: cntd [[CNT:x[0-9]+]]
Dsve-vscale-combine.ll14 ; CHECK-NEXT: cntd x0
24 ; CHECK-NEXT: cntd x0
Dsve-insert-vector.ll12 ; CHECK-NEXT: cntd x8
34 ; CHECK-NEXT: cntd x8
Dsve-extract-vector.ll24 ; CHECK-NEXT: cntd x8
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc4488 CntFn cntd = &MacroAssembler::Cntd; in TEST_SVE() local
4494 IncDecZHelper(config, &MacroAssembler::Decd, cntd, sub, mult, kDRegSize); in TEST_SVE()
4497 IncDecZHelper(config, &MacroAssembler::Incd, cntd, add, mult, kDRegSize); in TEST_SVE()
4504 CntFn cntd = &MacroAssembler::Cntd; in TEST_SVE() local
4510 IncDecZHelper(config, &MacroAssembler::Uqdecd, cntd, sub, mult, kDRegSize); in TEST_SVE()
4513 IncDecZHelper(config, &MacroAssembler::Uqincd, cntd, add, mult, kDRegSize); in TEST_SVE()
4520 CntFn cntd = &MacroAssembler::Cntd; in TEST_SVE() local
4526 IncDecZHelper(config, &MacroAssembler::Sqdecd, cntd, sub, mult, kDRegSize); in TEST_SVE()
4529 IncDecZHelper(config, &MacroAssembler::Sqincd, cntd, add, mult, kDRegSize); in TEST_SVE()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td846 defm CNTD_XPiI : sve_int_count<0b110, "cntd", int_aarch64_sve_cntd>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h3930 void cntd(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
Dassembler-sve-aarch64.cc450 V(cntd, CNTD_r_s) \
Dmacro-assembler-aarch64.h3949 cntd(rd, pattern, multiplier);
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1292 defm CNTD_XPiI : sve_int_count<0b110, "cntd", int_aarch64_sve_cntd>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12490 "cnot\003cnt\004cntb\004cntd\004cnth\004cntp\004cntw\007compact\003cpy\006"
13411 …{ 759 /* cntd */, AArch64::CNTD_XPiI, Convert__Reg1_0__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GP…
13412 …{ 759 /* cntd */, AArch64::CNTD_XPiI, Convert__Reg1_0__SVEPattern1_1__imm_95_1, AMFBS_HasSVE, { MC…
13413 …{ 759 /* cntd */, AArch64::CNTD_XPiI, Convert__Reg1_0__SVEPattern1_1__Imm1_161_3, AMFBS_HasSVE, { …
20784 …{ 759 /* cntd */, AArch64::CNTD_XPiI, Convert__Reg1_0__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GP…
20785 …{ 759 /* cntd */, AArch64::CNTD_XPiI, Convert__Reg1_0__SVEPattern1_1__imm_95_1, AMFBS_HasSVE, { MC…
20786 …{ 759 /* cntd */, AArch64::CNTD_XPiI, Convert__Reg1_0__SVEPattern1_1__Imm1_161_3, AMFBS_HasSVE, { …
29149 { 759 /* cntd */, 2 /* 1 */, MCK_SVEPattern, AMFBS_HasSVE },
29150 { 759 /* cntd */, 2 /* 1 */, MCK_SVEPattern, AMFBS_HasSVE },
29151 { 759 /* cntd */, 2 /* 1 */, MCK_SVEPattern, AMFBS_HasSVE },
[all …]
DAArch64GenAsmWriter.inc22133 /* 398 */ "cntd $\x01\0"
22134 /* 406 */ "cntd $\x01, $\xFF\x02\x0E\0"
DAArch64GenAsmWriter1.inc22854 /* 398 */ "cntd $\x01\0"
22855 /* 406 */ "cntd $\x01, $\xFF\x02\x0E\0"
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc554 "llvm.aarch64.sve.cntd",
10687 23, // llvm.aarch64.sve.cntd