/external/libdrm/tests/amdgpu/ |
D | vcn_tests.c | 52 uint32_t cntl; member 134 reg.cntl = 0x506; in suite_vcn_tests_enable() 140 reg.cntl = 0x81c6; in suite_vcn_tests_enable() 150 reg.cntl = 0x26d; in suite_vcn_tests_enable() 157 reg.cntl = 0x506; in suite_vcn_tests_enable() 164 reg.cntl = 0x26d; in suite_vcn_tests_enable() 409 ib_cpu[len++] = reg.cntl; in amdgpu_cs_vcn_dec_decode()
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/external/arm-trusted-firmware/fdts/ |
D | fvp-base-gicv2-psci.dts | 163 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
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D | fvp-base-gicv3-psci-aarch32-common.dtsi | 210 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
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D | fvp-base-gicv2-psci-aarch32.dts | 210 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
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D | fvp-base-gicv3-psci-common.dtsi | 225 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86InstrInfo.td | 2617 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2619 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2620 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>, 2623 (ins x86memop:$src1, immtype:$cntl), 2625 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2626 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>, 2696 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2697 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2698 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>, 2701 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), [all …]
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/external/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
D | fd6_gmem.c | 280 uint32_t cntl = 0; in update_render_cntl() local 303 cntl |= A6XX_RB_RENDER_CNTL_UNK4; in update_render_cntl() 305 cntl |= A6XX_RB_RENDER_CNTL_BINNING; in update_render_cntl() 310 OUT_RING(ring, cntl | in update_render_cntl()
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86InstrInfo.td | 2683 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2685 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2686 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>, 2689 (ins x86memop:$src1, immtype:$cntl), 2691 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2692 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>, 2762 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2763 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2764 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>, 2767 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), [all …]
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | radeon_uvd.c | 90 unsigned cntl; member 1199 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame() 1333 dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15; in si_common_uvd_create_decoder() 1338 dec->reg.cntl = RUVD_ENGINE_CNTL; in si_common_uvd_create_decoder()
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D | radeon_vcn_dec.h | 845 unsigned cntl; member
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D | radeon_vcn_dec.c | 1566 set_reg(dec, dec->reg.cntl, 1); in send_cmd_dec() 1720 dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL; in radeon_create_decoder() 1730 dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL; in radeon_create_decoder() 1741 dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL; in radeon_create_decoder()
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/external/mesa3d/src/gallium/drivers/r600/ |
D | radeon_uvd.c | 98 unsigned cntl; member 1018 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame() 1134 dec->reg.cntl = RUVD_ENGINE_CNTL; in ruvd_create_decoder()
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
D | r200_state.c | 208 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & in r200_set_blend_state() local 221 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; in r200_set_blend_state() 226 … rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE; in r200_set_blend_state() 229 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl; in r200_set_blend_state()
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/external/mesa3d/src/freedreno/vulkan/ |
D | tu_cmd_buffer.c | 326 uint32_t cntl = 0; in tu6_emit_render_cntl() local 327 cntl |= A6XX_RB_RENDER_CNTL_UNK4; in tu6_emit_render_cntl() 329 cntl |= A6XX_RB_RENDER_CNTL_BINNING; in tu6_emit_render_cntl() 342 cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable); in tu6_emit_render_cntl() 348 cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH; in tu6_emit_render_cntl() 366 tu_cs_emit(cs, cntl); in tu6_emit_render_cntl()
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/external/llvm/lib/Target/X86/ |
D | X86InstrInfo.td | 2354 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2356 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2357 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>, 2360 (ins x86memop:$src1, immtype:$cntl), 2362 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2363 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
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/external/capstone/arch/X86/ |
D | X86MappingInsnOp_reduce.inc | 524 { /* X86_BEXTRI32mi, X86_INS_BEXTR: bextr $dst, $src1, $cntl */ 528 { /* X86_BEXTRI32ri, X86_INS_BEXTR: bextr $dst, $src1, $cntl */ 532 { /* X86_BEXTRI64mi, X86_INS_BEXTR: bextr $dst, $src1, $cntl */ 536 { /* X86_BEXTRI64ri, X86_INS_BEXTR: bextr $dst, $src1, $cntl */
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D | X86MappingInsnOp.inc | 700 { /* X86_BEXTRI32mi, X86_INS_BEXTR: bextr $dst, $src1, $cntl */ 704 { /* X86_BEXTRI32ri, X86_INS_BEXTR: bextr $dst, $src1, $cntl */ 708 { /* X86_BEXTRI64mi, X86_INS_BEXTR: bextr $dst, $src1, $cntl */ 712 { /* X86_BEXTRI64ri, X86_INS_BEXTR: bextr $dst, $src1, $cntl */
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
D | X86GenGlobalISel.inc | 10115 // MIs[0] cntl 10117 …:$src1, (timm:{ *:[i32] }):$cntl) => (LWPVAL32rri GR32:{ *:[i32] }:$src0, GR32:{ *:[i32] }:$src1… 10121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cntl 10135 // MIs[0] cntl 10137 …:$src1, (timm:{ *:[i32] }):$cntl) => (LWPVAL64rri GR64:{ *:[i64] }:$src0, GR32:{ *:[i32] }:$src1… 10141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cntl
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