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Searched refs:cntw (Results 1 – 19 of 19) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dcntw-diagnostics.s6 cntw w0 label
11 cntw sp label
16 cntw z0.b label
25 cntw x0, all, mul #-1 label
30 cntw x0, all, mul #0 label
35 cntw x0, all, mul #17 label
44 cntw x0, #-1 label
49 cntw x0, #32 label
54 cntw x0, vl512 label
Dcntw.s10 cntw x0 label
16 cntw x0, all label
22 cntw x0, all, mul #1 label
28 cntw x0, all, mul #16 label
34 cntw x0, pow2 label
40 cntw x0, #28 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-counting-elems.ll71 define i64 @cntw() {
72 ; CHECK-LABEL: cntw:
73 ; CHECK: cntw x0, vl4
75 %out = call i64 @llvm.aarch64.sve.cntw(i32 4)
81 ; CHECK: cntw x0, vl8, mul #11
83 %cnt = call i64 @llvm.aarch64.sve.cntw(i32 8)
90 ; CHECK: cntw x0, vl6, mul #2
92 %cnt = call i64 @llvm.aarch64.sve.cntw(i32 6)
169 declare i64 @llvm.aarch64.sve.cntw(i32 %pattern)
Dsve-vscale.ll141 ; CHECK-LABEL: cntw:
142 ; CHECK: cntw x0{{$}}
144 define i32 @cntw() nounwind {
151 ; CHECK: cntw x0, all, mul #15
160 ; CHECK: cntw [[CNT:x[0-9]+]]
Dsve-insert-vector.ll56 ; CHECK-NEXT: cntw x8
78 ; CHECK-NEXT: cntw x8
Dsve-extract-vector.ll56 ; CHECK-NEXT: cntw x8
Dsve-split-extract-elt.ll203 ; CHECK-NEXT: cntw x10
/external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/AArch64/
Dvscale-factor-out-constant.ll15 %num_elm = call i64 @llvm.aarch64.sve.cntw(i32 31)
47 declare i64 @llvm.aarch64.sve.cntw(i32 immarg)
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc4487 CntFn cntw = &MacroAssembler::Cntw; in TEST_SVE() local
4493 IncDecZHelper(config, &MacroAssembler::Decw, cntw, sub, mult, kSRegSize); in TEST_SVE()
4496 IncDecZHelper(config, &MacroAssembler::Incw, cntw, add, mult, kSRegSize); in TEST_SVE()
4503 CntFn cntw = &MacroAssembler::Cntw; in TEST_SVE() local
4509 IncDecZHelper(config, &MacroAssembler::Uqdecw, cntw, sub, mult, kSRegSize); in TEST_SVE()
4512 IncDecZHelper(config, &MacroAssembler::Uqincw, cntw, add, mult, kSRegSize); in TEST_SVE()
4519 CntFn cntw = &MacroAssembler::Cntw; in TEST_SVE() local
4525 IncDecZHelper(config, &MacroAssembler::Sqdecw, cntw, sub, mult, kSRegSize); in TEST_SVE()
4528 IncDecZHelper(config, &MacroAssembler::Sqincw, cntw, add, mult, kSRegSize); in TEST_SVE()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td845 defm CNTW_XPiI : sve_int_count<0b100, "cntw", int_aarch64_sve_cntw>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h3941 void cntw(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
Dassembler-sve-aarch64.cc449 V(cntw, CNTW_r_s) \
Dmacro-assembler-aarch64.h3969 cntw(rd, pattern, multiplier);
/external/icu/icu4c/source/data/misc/
DsupplementalData.txt8624 "cntw",
20522 "cntw",
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1291 defm CNTW_XPiI : sve_int_count<0b100, "cntw", int_aarch64_sve_cntw>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12490 "cnot\003cnt\004cntb\004cntd\004cnth\004cntp\004cntw\007compact\003cpy\006"
13421 …{ 774 /* cntw */, AArch64::CNTW_XPiI, Convert__Reg1_0__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GP…
13422 …{ 774 /* cntw */, AArch64::CNTW_XPiI, Convert__Reg1_0__SVEPattern1_1__imm_95_1, AMFBS_HasSVE, { MC…
13423 …{ 774 /* cntw */, AArch64::CNTW_XPiI, Convert__Reg1_0__SVEPattern1_1__Imm1_161_3, AMFBS_HasSVE, { …
20794 …{ 774 /* cntw */, AArch64::CNTW_XPiI, Convert__Reg1_0__imm_95_31__imm_95_1, AMFBS_HasSVE, { MCK_GP…
20795 …{ 774 /* cntw */, AArch64::CNTW_XPiI, Convert__Reg1_0__SVEPattern1_1__imm_95_1, AMFBS_HasSVE, { MC…
20796 …{ 774 /* cntw */, AArch64::CNTW_XPiI, Convert__Reg1_0__SVEPattern1_1__Imm1_161_3, AMFBS_HasSVE, { …
29173 { 774 /* cntw */, 2 /* 1 */, MCK_SVEPattern, AMFBS_HasSVE },
29174 { 774 /* cntw */, 2 /* 1 */, MCK_SVEPattern, AMFBS_HasSVE },
29175 { 774 /* cntw */, 2 /* 1 */, MCK_SVEPattern, AMFBS_HasSVE },
[all …]
DAArch64GenAsmWriter.inc22137 /* 442 */ "cntw $\x01\0"
22138 /* 450 */ "cntw $\x01, $\xFF\x02\x0E\0"
DAArch64GenAsmWriter1.inc22858 /* 442 */ "cntw $\x01\0"
22859 /* 450 */ "cntw $\x01, $\xFF\x02\x0E\0"
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc557 "llvm.aarch64.sve.cntw",
10690 23, // llvm.aarch64.sve.cntw