| /external/tcpdump/tests/ |
| D | pimv2-oobr-4.out | 12 0x0000: 6900 1400 04d7 67b7 1400 0000 0400 0000
15 0x0030: 0200 6900 1400 04d7 67b7 1400 0000 0400
18 0x0060: 0000 0200 6900 1400 04d7 67b7 1400 0000
21 0x0090: 0000 0000 0200 6900 1400 04d7 67b7 1400
24 0x00c0: 0015 0000 0000 0200 6900 1400 04d7 67b7
27 0x00f0: 0001 0015 0000 0000 0200 6900 1400 04d7
31 0x0130: 04d7 67b7 1400 0000 0400 0000 0100 1500
34 0x0160: 1400 04d7 67b7 1400 0000 0400 0000 0100
37 0x0190: 6900 1400 04d7 67b7 1400 0000 0400 0000
40 0x01c0: 0200 6900 1400 04d7 67b7 1400 0000 0400
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | neon-bitwise-encoding.s | 169 vand d4, d7, d3
170 vand.8 d4, d7, d3
171 vand.16 d4, d7, d3
172 vand.32 d4, d7, d3
173 vand.64 d4, d7, d3
175 vand.i8 d4, d7, d3
176 vand.i16 d4, d7, d3
177 vand.i32 d4, d7, d3
178 vand.i64 d4, d7, d3
180 vand.s8 d4, d7, d3
[all …]
|
| D | neon-vld-encoding.s | 13 vld1.32 {d5, d6, d7}, [r3]
14 vld1.64 {d6, d7, d8}, [r3:64]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
18 vld1.64 {d6, d7, d8, d9}, [r3:64]
40 vld1.32 {d5, d6, d7}, [r3]!
41 vld1.64 {d6, d7, d8}, [r3:64]!
45 vld1.32 {d5, d6, d7}, [r3], r6
46 vld1.64 {d6, d7, d8}, [r3:64], r6
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
[all …]
|
| /external/capstone/suite/MC/ARM/ |
| D | neon-bitwise-encoding.s.cs | 46 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
47 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
48 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
49 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
50 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
51 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
52 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
53 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
54 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
55 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
[all …]
|
| D | neon-vld-encoding.s.cs | 12 0x8f,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]
13 0xdf,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64]
15 0x5f,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]
16 0x8f,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3]
17 0xdf,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64]
36 0x8d,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]!
37 0xdd,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64]!
40 0x86,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3], r6
41 0xd6,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64], r6
43 0x5d,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]!
[all …]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | neon-bitwise-encoding.s | 176 vand d4, d7, d3
177 vand.8 d4, d7, d3
178 vand.16 d4, d7, d3
179 vand.32 d4, d7, d3
180 vand.64 d4, d7, d3
182 vand.i8 d4, d7, d3
183 vand.i16 d4, d7, d3
184 vand.i32 d4, d7, d3
185 vand.i64 d4, d7, d3
187 vand.s8 d4, d7, d3
[all …]
|
| D | neon-vld-encoding.s | 13 vld1.32 {d5, d6, d7}, [r3]
14 vld1.64 {d6, d7, d8}, [r3:64]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
18 vld1.64 {d6, d7, d8, d9}, [r3:64]
40 vld1.32 {d5, d6, d7}, [r3]!
41 vld1.64 {d6, d7, d8}, [r3:64]!
45 vld1.32 {d5, d6, d7}, [r3], r6
46 vld1.64 {d6, d7, d8}, [r3:64], r6
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | float_arithmetic_operations.mir | 148 liveins: $d6, $d7
151 ; FP32: liveins: $d6, $d7
153 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
158 ; FP64: liveins: $d6, $d7
160 ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
165 %1:fprb(s64) = COPY $d7
179 liveins: $d6, $d7
182 ; FP32: liveins: $d6, $d7
184 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
189 ; FP64: liveins: $d6, $d7
[all …]
|
| D | fcmp.mir | 605 liveins: $d6, $d7
608 ; FP32: liveins: $d6, $d7
613 ; FP64: liveins: $d6, $d7
631 liveins: $d6, $d7
634 ; FP32: liveins: $d6, $d7
639 ; FP64: liveins: $d6, $d7
657 liveins: $d6, $d7
660 ; FP32: liveins: $d6, $d7
662 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
669 ; FP64: liveins: $d6, $d7
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ |
| D | float_arithmetic_operations.mir | 139 liveins: $d6, $d7
142 ; FP32: liveins: $d6, $d7
144 ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
149 ; FP64: liveins: $d6, $d7
151 ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
156 %1:_(s64) = COPY $d7
168 liveins: $d6, $d7
171 ; FP32: liveins: $d6, $d7
173 ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
178 ; FP64: liveins: $d6, $d7
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ |
| D | float_arithmetic_operations.mir | 144 liveins: $d6, $d7
147 ; FP32: liveins: $d6, $d7
149 ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
154 ; FP64: liveins: $d6, $d7
156 ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
161 %1:_(s64) = COPY $d7
174 liveins: $d6, $d7
177 ; FP32: liveins: $d6, $d7
179 ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
184 ; FP64: liveins: $d6, $d7
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_inter_pred_chroma_vert_w16out.s | 191 vdup.32 d7,d6[1]
192 vld1.32 {d7[1]},[r6],r2 @loads pu1_src_tmp
193 vmull.u8 q2,d7,d1 @vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1)
194 vdup.32 d7,d7[1]
195 vld1.32 {d7[1]},[r6],r2
197 vmlal.u8 q2,d7,d2
198 vdup.32 d7,d7[1]
199 vld1.32 {d7[1]},[r6]
201 vmlsl.u8 q2,d7,d3
238 vld1.8 {d7},[r6],r2 @load and increment
[all …]
|
| D | ihevc_inter_pred_chroma_vert.s | 192 vdup.32 d7,d6[1]
193 vld1.32 {d7[1]},[r6],r2 @loads pu1_src_tmp
194 vmull.u8 q2,d7,d1 @vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1)
195 vdup.32 d7,d7[1]
196 vld1.32 {d7[1]},[r6],r2
198 vmlal.u8 q2,d7,d2
199 vdup.32 d7,d7[1]
200 vld1.32 {d7[1]},[r6]
202 vmlsl.u8 q2,d7,d3
239 vld1.8 {d7},[r6],r2 @load and increment
[all …]
|
| D | ihevc_intra_pred_luma_planar.s | 154 …vmov d7, d5 @mov #1 to d7 to used for inc for row+1 and dec for nt-1-r…
202 vadd.s8 d5, d5, d7 @(1)
204 vsub.s8 d6, d6, d7 @(1)
217 vadd.s8 d5, d5, d7 @(2)
218 vsub.s8 d6, d6, d7 @(2)
234 vadd.s8 d5, d5, d7 @(3)
235 vsub.s8 d6, d6, d7 @(3)
251 vadd.s8 d5, d5, d7 @(4)
252 vsub.s8 d6, d6, d7 @(4)
267 vadd.s8 d5, d5, d7 @(5)
[all …]
|
| D | ihevc_padding.s | 146 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
147 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
148 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
149 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
150 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
265 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
266 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
267 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
268 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
269 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
[all …]
|
| D | ihevc_itrans_recon_32x32.s | 122 @d5[0]= 50 d7[0]=18
123 @d5[1]= 46 d7[1]=13
124 @d5[2]= 43 d7[2]=9
125 @d5[3]= 38 d7[3]=4
178 vld1.16 {d4,d5,d6,d7},[r14]!
260 vmlsl.s16 q15,d14,d7[1]
265 vmlsl.s16 q14,d15,d7[1]
274 vmlal.s16 q8,d13,d7[2]
275 vmlal.s16 q9,d12,d7[0]
293 vmlsl.s16 q13,d9,d7[3] @// y1 * cos3 - y3 * sin1(part of b1)
[all …]
|
| D | ihevc_itrans_recon_16x16.s | 226 vld1.16 d7,[r9],r10
240 @d7=r3
248 vmlal.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0)
249 vmlal.s16 q13,d7,d2[1] @// y1 * cos3 - y3 * sin1(part of b1)
250 vmlal.s16 q14,d7,d3[3] @// y1 * sin3 - y3 * cos1(part of b2)
251 vmlsl.s16 q15,d7,d2[3] @// y1 * sin1 - y3 * sin3(part of b3)
309 vld1.16 d7,[r9],r10
323 vmlal.s16 q12,d7,d2[3] @// y1 * cos1 + y3 * cos3(part of b0)
324 vmlsl.s16 q13,d7,d0[1] @// y1 * cos3 - y3 * sin1(part of b1)
325 vmlal.s16 q14,d7,d2[1] @// y1 * sin3 - y3 * cos1(part of b2)
[all …]
|
| /external/rust/crates/ring/pregenerated/ |
| D | ghash-armv4-ios32.S | 41 vld1.64 d7,[r1]! @ load H
46 vdup.8 q9,d7[7]
51 vorr d7,d26 @ H<<<=1
65 vld1.64 d7,[r0]! @ load Xi
98 vld1.64 d7,[r2]! @ load inp
142 veor d6,d6,d7 @ Karatsuba pre-processing
181 vmull.p8 q8, d16, d7 @ F = A1*B
182 vext.8 d4, d7, d7, #1 @ B1
185 vmull.p8 q9, d18, d7 @ H = A2*B
186 vext.8 d22, d7, d7, #2 @ B2
[all …]
|
| D | ghash-armv4-linux32.S | 40 vld1.64 d7,[r1]! @ load H
45 vdup.8 q9,d7[7]
50 vorr d7,d26 @ H<<<=1
62 vld1.64 d7,[r0]! @ load Xi
93 vld1.64 d7,[r2]! @ load inp
137 veor d6,d6,d7 @ Karatsuba pre-processing
176 vmull.p8 q8, d16, d7 @ F = A1*B
177 vext.8 d4, d7, d7, #1 @ B1
180 vmull.p8 q9, d18, d7 @ H = A2*B
181 vext.8 d22, d7, d7, #2 @ B2
[all …]
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | ghash-armv4.S | 44 vld1.64 d7,[r1]! @ load H
49 vdup.8 q9,d7[7]
54 vorr d7,d26 @ H<<<=1
68 vld1.64 d7,[r0]! @ load Xi
101 vld1.64 d7,[r2]! @ load inp
145 veor d6,d6,d7 @ Karatsuba pre-processing
184 vmull.p8 q8, d16, d7 @ F = A1*B
185 vext.8 d4, d7, d7, #1 @ B1
188 vmull.p8 q9, d18, d7 @ H = A2*B
189 vext.8 d22, d7, d7, #2 @ B2
[all …]
|
| /external/rust/crates/quiche/deps/boringssl/linux-arm/crypto/fipsmodule/ |
| D | ghash-armv4.S | 43 vld1.64 d7,[r1]! @ load H
48 vdup.8 q9,d7[7]
53 vorr d7,d26 @ H<<<=1
65 vld1.64 d7,[r0]! @ load Xi
96 vld1.64 d7,[r2]! @ load inp
140 veor d6,d6,d7 @ Karatsuba pre-processing
179 vmull.p8 q8, d16, d7 @ F = A1*B
180 vext.8 d4, d7, d7, #1 @ B1
183 vmull.p8 q9, d18, d7 @ H = A2*B
184 vext.8 d22, d7, d7, #2 @ B2
[all …]
|
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | ghash-armv4.S | 43 vld1.64 d7,[r1]! @ load H
48 vdup.8 q9,d7[7]
53 vorr d7,d26 @ H<<<=1
65 vld1.64 d7,[r0]! @ load Xi
96 vld1.64 d7,[r2]! @ load inp
140 veor d6,d6,d7 @ Karatsuba pre-processing
179 vmull.p8 q8, d16, d7 @ F = A1*B
180 vext.8 d4, d7, d7, #1 @ B1
183 vmull.p8 q9, d18, d7 @ H = A2*B
184 vext.8 d22, d7, d7, #2 @ B2
[all …]
|
| /external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/ |
| D | ghash-armv4.S | 44 vld1.64 d7,[r1]! @ load H
49 vdup.8 q9,d7[7]
54 vorr d7,d26 @ H<<<=1
68 vld1.64 d7,[r0]! @ load Xi
101 vld1.64 d7,[r2]! @ load inp
145 veor d6,d6,d7 @ Karatsuba pre-processing
184 vmull.p8 q8, d16, d7 @ F = A1*B
185 vext.8 d4, d7, d7, #1 @ B1
188 vmull.p8 q9, d18, d7 @ H = A2*B
189 vext.8 d22, d7, d7, #2 @ B2
[all …]
|
| /external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/ |
| D | ghash-armv4.S | 44 vld1.64 d7,[r1]! @ load H
49 vdup.8 q9,d7[7]
54 vorr d7,d26 @ H<<<=1
68 vld1.64 d7,[r0]! @ load Xi
101 vld1.64 d7,[r2]! @ load inp
145 veor d6,d6,d7 @ Karatsuba pre-processing
184 vmull.p8 q8, d16, d7 @ F = A1*B
185 vext.8 d4, d7, d7, #1 @ B1
188 vmull.p8 q9, d18, d7 @ H = A2*B
189 vext.8 d22, d7, d7, #2 @ B2
[all …]
|
| /external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/ |
| D | ghash-armv4.S | 43 vld1.64 d7,[r1]! @ load H
48 vdup.8 q9,d7[7]
53 vorr d7,d26 @ H<<<=1
65 vld1.64 d7,[r0]! @ load Xi
96 vld1.64 d7,[r2]! @ load inp
140 veor d6,d6,d7 @ Karatsuba pre-processing
179 vmull.p8 q8, d16, d7 @ F = A1*B
180 vext.8 d4, d7, d7, #1 @ B1
183 vmull.p8 q9, d18, d7 @ H = A2*B
184 vext.8 d22, d7, d7, #2 @ B2
[all …]
|