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/external/llvm-project/llvm/test/CodeGen/WebAssembly/
Dreg-stackify.ll251 ; CHECK-NEXT: i32.div_s $push[[L0:[0-9]+]]=, $0, $1{{$}}
252 ; CHECK-NEXT: i32.div_s $push[[L1:[0-9]+]]=, $2, $3{{$}}
253 ; CHECK-NEXT: i32.div_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
254 ; CHECK-NEXT: i32.div_s $push[[L3:[0-9]+]]=, $4, $5{{$}}
255 ; CHECK-NEXT: i32.div_s $push[[L4:[0-9]+]]=, $6, $7{{$}}
256 ; CHECK-NEXT: i32.div_s $push[[L5:[0-9]+]]=, $pop[[L3]], $pop[[L4]]{{$}}
257 ; CHECK-NEXT: i32.div_s $push[[L6:[0-9]+]]=, $pop[[L2]], $pop[[L5]]{{$}}
258 ; CHECK-NEXT: i32.div_s $push[[L7:[0-9]+]]=, $8, $9{{$}}
259 ; CHECK-NEXT: i32.div_s $push[[L8:[0-9]+]]=, $10, $11{{$}}
260 ; CHECK-NEXT: i32.div_s $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
[all …]
Ddivrem-constant.ll23 ; CHECK: i32.div_s
30 ; CHECK: i32.div_s
Dphi.ll11 ; CHECK: div_s $[[NUM0:[0-9]+]]=, $0, $pop[[NUM1:[0-9]+]]{{$}}
Dsimd-unsupported.ll53 ; CHECK: i32.div_s
142 ; CHECK: i32.div_s
231 ; CHECK: i32.div_s
320 ; CHECK: i64.div_s
/external/llvm/test/CodeGen/WebAssembly/
Dreg-stackify.ll188 ; CHECK-NEXT: i32.div_s $push[[L0:[0-9]+]]=, $0, $1{{$}}
189 ; CHECK-NEXT: i32.div_s $push[[L1:[0-9]+]]=, $2, $3{{$}}
190 ; CHECK-NEXT: i32.div_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
191 ; CHECK-NEXT: i32.div_s $push[[L3:[0-9]+]]=, $4, $5{{$}}
192 ; CHECK-NEXT: i32.div_s $push[[L4:[0-9]+]]=, $6, $7{{$}}
193 ; CHECK-NEXT: i32.div_s $push[[L5:[0-9]+]]=, $pop[[L3]], $pop[[L4]]{{$}}
194 ; CHECK-NEXT: i32.div_s $push[[L6:[0-9]+]]=, $pop[[L2]], $pop[[L5]]{{$}}
195 ; CHECK-NEXT: i32.div_s $push[[L7:[0-9]+]]=, $8, $9{{$}}
196 ; CHECK-NEXT: i32.div_s $push[[L8:[0-9]+]]=, $10, $11{{$}}
197 ; CHECK-NEXT: i32.div_s $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
[all …]
Ddivrem-constant.ll23 ; CHECK: i32.div_s
30 ; CHECK: i32.div_s
Dphi.ll11 ; CHECK: div_s $[[NUM0:[0-9]+]]=, $0, $pop[[NUM1:[0-9]+]]{{$}}
/external/llvm/test/CodeGen/Mips/msa/
D3r-d.ll25 ; CHECK: div_s.b
47 ; CHECK: div_s.h
69 ; CHECK: div_s.w
91 ; CHECK: div_s.d
108 ; CHECK: div_s.b
124 ; CHECK: div_s.h
140 ; CHECK: div_s.w
156 ; CHECK: div_s.d
Darithmetic.ll480 ; CHECK-DAG: div_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
496 ; CHECK-DAG: div_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
512 ; CHECK-DAG: div_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
528 ; CHECK-DAG: div_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D3r-d.ll25 ; CHECK: div_s.b
47 ; CHECK: div_s.h
69 ; CHECK: div_s.w
91 ; CHECK: div_s.d
108 ; CHECK: div_s.b
124 ; CHECK: div_s.h
140 ; CHECK: div_s.w
156 ; CHECK: div_s.d
Darithmetic.ll514 ; ALL-NEXT: div_s.b $w0, $w1, $w0
529 ; ALL-NEXT: div_s.h $w0, $w1, $w0
544 ; ALL-NEXT: div_s.w $w0, $w1, $w0
559 ; ALL-NEXT: div_s.d $w0, $w1, $w0
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Drem_and_div_vec.ll9 ; P5600-NEXT: div_s.b $w0, $w0, $w1
26 ; P5600-NEXT: div_s.h $w0, $w0, $w1
43 ; P5600-NEXT: div_s.w $w0, $w0, $w1
60 ; P5600-NEXT: div_s.d $w0, $w0, $w1
Drem_and_div_vec_builtin.ll10 ; P5600-NEXT: div_s.b $w0, $w0, $w1
28 ; P5600-NEXT: div_s.h $w0, $w0, $w1
46 ; P5600-NEXT: div_s.w $w0, $w0, $w1
64 ; P5600-NEXT: div_s.d $w0, $w0, $w1
/external/capstone/suite/MC/Mips/
Dtest_3r.s.cs86 0x7a,0x12,0x1f,0x52 = div_s.b $w29, $w3, $w18
87 0x7a,0x2d,0x84,0x52 = div_s.h $w17, $w16, $w13
88 0x7a,0x5e,0xc9,0x12 = div_s.w $w4, $w25, $w30
89 0x7a,0x74,0x4f,0xd2 = div_s.d $w31, $w9, $w20
/external/llvm-project/llvm/test/CodeGen/Generic/
Dprint-arith-fp.ll35 %div_s = getelementptr [12 x i8], [12 x i8]* @div_str, i64 0, i64 0 ; <i8*> [#uses=1]
40 call i32 (i8*, ...) @printf( i8* %div_s, double %div_r ) ; <i32>:6 [#uses=0]
Dprint-arith-int.ll40 %div_s = getelementptr [12 x i8], [12 x i8]* @div_str, i64 0, i64 0 ; <i8*> [#uses=1]
45 call i32 (i8*, ...) @printf( i8* %div_s, i32 %div_r ) ; <i32>:6 [#uses=0]
/external/llvm/test/CodeGen/Generic/
Dprint-arith-fp.ll35 %div_s = getelementptr [12 x i8], [12 x i8]* @div_str, i64 0, i64 0 ; <i8*> [#uses=1]
40 call i32 (i8*, ...) @printf( i8* %div_s, double %div_r ) ; <i32>:6 [#uses=0]
Dprint-arith-int.ll40 %div_s = getelementptr [12 x i8], [12 x i8]* @div_str, i64 0, i64 0 ; <i8*> [#uses=1]
45 call i32 (i8*, ...) @printf( i8* %div_s, i32 %div_r ) ; <i32>:6 [#uses=0]
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s87 # CHECK: div_s.b $w29, $w3, $w18 # encoding: [0x7a,0x12,0x1f,0x52]
88 # CHECK: div_s.h $w17, $w16, $w13 # encoding: [0x7a,0x2d,0x84,0x52]
89 # CHECK: div_s.w $w4, $w25, $w30 # encoding: [0x7a,0x5e,0xc9,0x12]
90 # CHECK: div_s.d $w31, $w9, $w20 # encoding: [0x7a,0x74,0x4f,0xd2]
330 div_s.b $w29, $w3, $w18
331 div_s.h $w17, $w16, $w13
332 div_s.w $w4, $w25, $w30
333 div_s.d $w31, $w9, $w20
/external/llvm-project/llvm/test/MC/Mips/msa/
Dtest_3r.s87 # CHECK: div_s.b $w29, $w3, $w18 # encoding: [0x7a,0x12,0x1f,0x52]
88 # CHECK: div_s.h $w17, $w16, $w13 # encoding: [0x7a,0x2d,0x84,0x52]
89 # CHECK: div_s.w $w4, $w25, $w30 # encoding: [0x7a,0x5e,0xc9,0x12]
90 # CHECK: div_s.d $w31, $w9, $w20 # encoding: [0x7a,0x74,0x4f,0xd2]
330 div_s.b $w29, $w3, $w18
331 div_s.h $w17, $w16, $w13
332 div_s.w $w4, $w25, $w30
333 div_s.d $w31, $w9, $w20
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt87 0x7a 0x12 0x1f 0x52 # CHECK: div_s.b $w29, $w3, $w18
88 0x7a 0x2d 0x84 0x52 # CHECK: div_s.h $w17, $w16, $w13
89 0x7a 0x5e 0xc9 0x12 # CHECK: div_s.w $w4, $w25, $w30
90 0x7a 0x74 0x4f 0xd2 # CHECK: div_s.d $w31, $w9, $w20
/external/llvm-project/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt87 0x7a 0x12 0x1f 0x52 # CHECK: div_s.b $w29, $w3, $w18
88 0x7a 0x2d 0x84 0x52 # CHECK: div_s.h $w17, $w16, $w13
89 0x7a 0x5e 0xc9 0x12 # CHECK: div_s.w $w4, $w25, $w30
90 0x7a 0x74 0x4f 0xd2 # CHECK: div_s.d $w31, $w9, $w20
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td26 defm DIV_S : BinaryInt<sdiv, "div_s">;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td56 defm DIV_S : BinaryInt<sdiv, "div_s", 0x6d, 0x7f>;
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td56 defm DIV_S : BinaryInt<sdiv, "div_s", 0x6d, 0x7f>;

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