| /external/llvm/test/CodeGen/ARM/ |
| D | optimize-dmbs-v7.ll | 23 ; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
26 ; CHECK: dmb
27 ; CHECK-NOT: dmb
31 ; CHECK: dmb
32 ; CHECK-NOT: dmb
36 ; CHECK: dmb
37 ; CHECK-NOT: dmb
41 ; CHECK: dmb
42 ; CHECK-NOT: dmb
48 call void @llvm.arm.dmb(i32 11)
[all …]
|
| D | atomic-load-store.ll | 11 ; ARM: dmb {{ish$}}
13 ; ARM-NEXT: dmb {{ish$}}
17 ; THUMBTWO: dmb {{ish$}}
19 ; THUMBTWO-NEXT: dmb {{ish$}}
25 ; THUMBM: dmb sy
27 ; THUMBM: dmb sy
35 ; ARM-NEXT: dmb {{ish$}}
40 ; THUMBTWO-NEXT: dmb {{ish$}}
46 ; THUMBM: dmb sy
53 ; ARM-NOT: dmb
[all …]
|
| D | swift-atomics.ll | 4 ; Release operations only need the store barrier provided by a "dmb ishst",
8 ; CHECK: dmb ishst
12 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
18 ; followed by an acquire does not get reordered. In that case a "dmb ishst" is
22 ; CHECK: dmb ishst
24 ; CHECK: dmb {{ish$}}
26 ; CHECK: dmb {{ish$}}
29 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
31 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
33 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
[all …]
|
| D | atomic-64bit.ll | 8 ; CHECK: dmb {{ish$}}
17 ; CHECK: dmb {{ish$}}
20 ; CHECK-THUMB: dmb {{ish$}}
29 ; CHECK-THUMB: dmb {{ish$}}
37 ; CHECK: dmb {{ish$}}
46 ; CHECK: dmb {{ish$}}
49 ; CHECK-THUMB: dmb {{ish$}}
58 ; CHECK-THUMB: dmb {{ish$}}
66 ; CHECK: dmb {{ish$}}
75 ; CHECK: dmb {{ish$}}
[all …]
|
| D | atomic-ops-v8.ll | 14 ; CHECK-NOT: dmb
27 ; CHECK-NOT: dmb
37 ; CHECK-NOT: dmb
50 ; CHECK-NOT: dmb
60 ; CHECK-NOT: dmb
73 ; CHECK-NOT: dmb
83 ; CHECK-NOT: dmb
99 ; CHECK-NOT: dmb
110 ; CHECK-NOT: dmb
123 ; CHECK-NOT: dmb
[all …]
|
| D | intrinsics-v8.ll | 4 ; CHECK: dmb sy
5 call void @llvm.arm.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.arm.dmb(i32 3)
17 declare void @llvm.arm.dmb(i32)
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | optimize-dmbs-v7.ll | 23 ; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
26 ; CHECK: dmb
27 ; CHECK-NOT: dmb
31 ; CHECK: dmb
32 ; CHECK-NOT: dmb
36 ; CHECK: dmb
37 ; CHECK-NOT: dmb
41 ; CHECK: dmb
42 ; CHECK-NOT: dmb
48 call void @llvm.arm.dmb(i32 11)
[all …]
|
| D | atomic-load-store.ll | 11 ; ARM: dmb {{ish$}}
13 ; ARM-NEXT: dmb {{ish$}}
17 ; THUMBTWO: dmb {{ish$}}
19 ; THUMBTWO-NEXT: dmb {{ish$}}
25 ; THUMBM: dmb sy
27 ; THUMBM: dmb sy
35 ; ARM-NEXT: dmb {{ish$}}
40 ; THUMBTWO-NEXT: dmb {{ish$}}
46 ; THUMBM: dmb sy
53 ; ARM-NOT: dmb
[all …]
|
| D | swift-atomics.ll | 4 ; Release operations only need the store barrier provided by a "dmb ishst",
8 ; CHECK: dmb ishst
12 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
18 ; followed by an acquire does not get reordered. In that case a "dmb ishst" is
22 ; CHECK: dmb ishst
24 ; CHECK: dmb {{ish$}}
26 ; CHECK: dmb {{ish$}}
29 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
31 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
33 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
[all …]
|
| D | atomic-64bit.ll | 8 ; CHECK: dmb {{ish$}}
17 ; CHECK: dmb {{ish$}}
20 ; CHECK-THUMB: dmb {{ish$}}
29 ; CHECK-THUMB: dmb {{ish$}}
37 ; CHECK: dmb {{ish$}}
46 ; CHECK: dmb {{ish$}}
49 ; CHECK-THUMB: dmb {{ish$}}
58 ; CHECK-THUMB: dmb {{ish$}}
66 ; CHECK: dmb {{ish$}}
75 ; CHECK: dmb {{ish$}}
[all …]
|
| D | atomic-ops-v8.ll | 14 ; CHECK-NOT: dmb
27 ; CHECK-NOT: dmb
37 ; CHECK-NOT: dmb
50 ; CHECK-NOT: dmb
60 ; CHECK-NOT: dmb
73 ; CHECK-NOT: dmb
83 ; CHECK-NOT: dmb
99 ; CHECK-NOT: dmb
110 ; CHECK-NOT: dmb
123 ; CHECK-NOT: dmb
[all …]
|
| D | intrinsics-v8.ll | 4 ; CHECK: dmb sy
5 call void @llvm.arm.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.arm.dmb(i32 3)
17 declare void @llvm.arm.dmb(i32)
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops.ll | 18 ; CHECK-NOT: dmb
29 ; CHECK-NOT: dmb
38 ; CHECK-NOT: dmb
49 ; CHECK-NOT: dmb
58 ; CHECK-NOT: dmb
69 ; CHECK-NOT: dmb
78 ; CHECK-NOT: dmb
89 ; CHECK-NOT: dmb
98 ; CHECK-NOT: dmb
109 ; CHECK-NOT: dmb
[all …]
|
| D | intrinsics-memory-barrier.ll | 4 ; CHECK: dmb sy
5 call void @llvm.aarch64.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.aarch64.dmb(i32 3)
23 call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy
55 declare void @llvm.aarch64.dmb(i32)
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions-v8.s | 22 dmb ishld
23 dmb oshld
24 dmb nshld
25 dmb ld
27 @ CHECK-V8: dmb ishld @ encoding: [0x59,0xf0,0x7f,0xf5]
28 @ CHECK-V8: dmb oshld @ encoding: [0x51,0xf0,0x7f,0xf5]
29 @ CHECK-V8: dmb nshld @ encoding: [0x55,0xf0,0x7f,0xf5]
30 @ CHECK-V8: dmb ld @ encoding: [0x5d,0xf0,0x7f,0xf5]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions-v8.s | 22 dmb ishld
23 dmb oshld
24 dmb nshld
25 dmb ld
27 @ CHECK-V8: dmb ishld @ encoding: [0x59,0xf0,0x7f,0xf5]
28 @ CHECK-V8: dmb oshld @ encoding: [0x51,0xf0,0x7f,0xf5]
29 @ CHECK-V8: dmb nshld @ encoding: [0x55,0xf0,0x7f,0xf5]
30 @ CHECK-V8: dmb ld @ encoding: [0x5d,0xf0,0x7f,0xf5]
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops-lse.ll | 30 ; CHECK-NOT: dmb
35 ; CHECK-NOT: dmb
51 ; CHECK-NOT: dmb
56 ; CHECK-NOT: dmb
72 ; CHECK-NOT: dmb
77 ; CHECK-NOT: dmb
93 ; CHECK-NOT: dmb
98 ; CHECK-NOT: dmb
114 ; CHECK-NOT: dmb
119 ; CHECK-NOT: dmb
[all …]
|
| D | atomic-ops.ll | 27 ; CHECK-NOT: dmb
38 ; CHECK-NOT: dmb
55 ; CHECK-NOT: dmb
66 ; CHECK-NOT: dmb
83 ; CHECK-NOT: dmb
94 ; CHECK-NOT: dmb
111 ; CHECK-NOT: dmb
122 ; CHECK-NOT: dmb
140 ; CHECK-NOT: dmb
151 ; CHECK-NOT: dmb
[all …]
|
| D | fence-singlethread.ll | 6 ; OBJ-NOT: dmb
10 ; LINUX-NOT: dmb
12 ; LINUX-NOT: dmb
15 ; IOS-NOT: dmb
17 ; IOS-NOT: dmb
|
| D | intrinsics-memory-barrier.ll | 4 ; CHECK: dmb sy
5 call void @llvm.aarch64.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.aarch64.dmb(i32 3)
23 call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy
55 declare void @llvm.aarch64.dmb(i32)
|
| /external/llvm-project/llvm/test/Transforms/AtomicExpand/ARM/ |
| D | atomic-expansion-v7.ll | 5 ; CHECK-NOT: dmb
15 ; CHECK-NOT: dmb
23 ; CHECK: call void @llvm.arm.dmb(i32 11)
34 ; CHECK: call void @llvm.arm.dmb(i32 11)
42 ; CHECK-NOT: dmb
51 ; CHECK: call void @llvm.arm.dmb(i32 11)
59 ; CHECK: call void @llvm.arm.dmb(i32 11)
70 ; CHECK-NOT: dmb
78 ; CHECK: call void @llvm.arm.dmb(i32 11)
90 ; CHECK: call void @llvm.arm.dmb(i32 11)
[all …]
|
| /external/llvm/test/Transforms/AtomicExpand/ARM/ |
| D | atomic-expansion-v7.ll | 5 ; CHECK-NOT: dmb
15 ; CHECK-NOT: dmb
23 ; CHECK: call void @llvm.arm.dmb(i32 11)
34 ; CHECK: call void @llvm.arm.dmb(i32 11)
42 ; CHECK-NOT: dmb
51 ; CHECK: call void @llvm.arm.dmb(i32 11)
59 ; CHECK: call void @llvm.arm.dmb(i32 11)
70 ; CHECK-NOT: dmb
78 ; CHECK: call void @llvm.arm.dmb(i32 11)
90 ; CHECK: call void @llvm.arm.dmb(i32 11)
[all …]
|
| D | cmpxchg-weak.ll | 5 ; Intrinsic for "dmb ishst" is then expected
14 ; CHECK: call void @llvm.arm.dmb(i32 10)
23 ; CHECK: call void @llvm.arm.dmb(i32 11)
31 ; CHECK: call void @llvm.arm.dmb(i32 11)
53 ; CHECK: call void @llvm.arm.dmb(i32 10)
62 ; CHECK: call void @llvm.arm.dmb(i32 11)
70 ; CHECK-NOT: dmb
84 ; CHECK-NOT: dmb
98 ; CHECK-NOT: dmb
106 ; CHECK-NOT: dmb
[all …]
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions-v8.s.cs | 2 0x59,0xf0,0x7f,0xf5 = dmb ishld
3 0x51,0xf0,0x7f,0xf5 = dmb oshld
4 0x55,0xf0,0x7f,0xf5 = dmb nshld
5 0x5d,0xf0,0x7f,0xf5 = dmb ld
|
| /external/llvm-project/llvm/test/tools/llvm-objdump/ELF/ARM/ |
| D | v6m-subarch.s | 5 dmb: label
6 dmb label
8 @ CHECK-LABEL: dmb
9 @ CHECK: bf f3 5f 8f dmb sy
|