1; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-expand -codegen-opt-level=1 %s | FileCheck %s 2 3define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) { 4; CHECK-LABEL: @test_atomic_xchg_i8 5; CHECK-NOT: dmb 6; CHECK: br label %[[LOOP:.*]] 7; CHECK: [[LOOP]]: 8; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 9; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 10; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32 11; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 12; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 13; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 14; CHECK: [[END]]: 15; CHECK-NOT: dmb 16; CHECK: ret i8 [[OLDVAL]] 17 %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic 18 ret i8 %res 19} 20 21define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) { 22; CHECK-LABEL: @test_atomic_add_i16 23; CHECK: call void @llvm.arm.dmb(i32 11) 24; CHECK: br label %[[LOOP:.*]] 25; CHECK: [[LOOP]]: 26; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) 27; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 28; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend 29; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 30; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) 31; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 32; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 33; CHECK: [[END]]: 34; CHECK: call void @llvm.arm.dmb(i32 11) 35; CHECK: ret i16 [[OLDVAL]] 36 %res = atomicrmw add i16* %ptr, i16 %addend seq_cst 37 ret i16 %res 38} 39 40define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) { 41; CHECK-LABEL: @test_atomic_sub_i32 42; CHECK-NOT: dmb 43; CHECK: br label %[[LOOP:.*]] 44; CHECK: [[LOOP]]: 45; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr) 46; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend 47; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* %ptr) 48; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 49; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 50; CHECK: [[END]]: 51; CHECK: call void @llvm.arm.dmb(i32 11) 52; CHECK: ret i32 [[OLDVAL]] 53 %res = atomicrmw sub i32* %ptr, i32 %subend acquire 54 ret i32 %res 55} 56 57define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) { 58; CHECK-LABEL: @test_atomic_and_i8 59; CHECK: call void @llvm.arm.dmb(i32 11) 60; CHECK: br label %[[LOOP:.*]] 61; CHECK: [[LOOP]]: 62; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 63; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 64; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend 65; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 66; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 67; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 68; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 69; CHECK: [[END]]: 70; CHECK-NOT: dmb 71; CHECK: ret i8 [[OLDVAL]] 72 %res = atomicrmw and i8* %ptr, i8 %andend release 73 ret i8 %res 74} 75 76define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) { 77; CHECK-LABEL: @test_atomic_nand_i16 78; CHECK: call void @llvm.arm.dmb(i32 11) 79; CHECK: br label %[[LOOP:.*]] 80; CHECK: [[LOOP]]: 81; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) 82; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 83; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend 84; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1 85; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 86; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) 87; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 88; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 89; CHECK: [[END]]: 90; CHECK: call void @llvm.arm.dmb(i32 11) 91; CHECK: ret i16 [[OLDVAL]] 92 %res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst 93 ret i16 %res 94} 95 96define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) { 97; CHECK-LABEL: @test_atomic_or_i64 98; CHECK: call void @llvm.arm.dmb(i32 11) 99; CHECK: br label %[[LOOP:.*]] 100; CHECK: [[LOOP]]: 101; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* 102; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) 103; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 104; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 105; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 106; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64 107; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 108; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] 109; CHECK: [[NEWVAL:%.*]] = or i64 [[OLDVAL]], %orend 110; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32 111; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32 112; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 113; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* 114; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) 115; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 116; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 117; CHECK: [[END]]: 118; CHECK: call void @llvm.arm.dmb(i32 11) 119; CHECK: ret i64 [[OLDVAL]] 120 %res = atomicrmw or i64* %ptr, i64 %orend seq_cst 121 ret i64 %res 122} 123 124define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) { 125; CHECK-LABEL: @test_atomic_xor_i8 126; CHECK: call void @llvm.arm.dmb(i32 11) 127; CHECK: br label %[[LOOP:.*]] 128; CHECK: [[LOOP]]: 129; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 130; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 131; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend 132; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 133; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 134; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 135; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 136; CHECK: [[END]]: 137; CHECK: call void @llvm.arm.dmb(i32 11) 138; CHECK: ret i8 [[OLDVAL]] 139 %res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst 140 ret i8 %res 141} 142 143define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) { 144; CHECK-LABEL: @test_atomic_max_i8 145; CHECK: call void @llvm.arm.dmb(i32 11) 146; CHECK: br label %[[LOOP:.*]] 147; CHECK: [[LOOP]]: 148; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 149; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 150; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend 151; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend 152; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 153; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 154; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 155; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 156; CHECK: [[END]]: 157; CHECK: call void @llvm.arm.dmb(i32 11) 158; CHECK: ret i8 [[OLDVAL]] 159 %res = atomicrmw max i8* %ptr, i8 %maxend seq_cst 160 ret i8 %res 161} 162 163define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) { 164; CHECK-LABEL: @test_atomic_min_i8 165; CHECK: call void @llvm.arm.dmb(i32 11) 166; CHECK: br label %[[LOOP:.*]] 167; CHECK: [[LOOP]]: 168; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 169; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 170; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend 171; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend 172; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 173; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 174; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 175; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 176; CHECK: [[END]]: 177; CHECK: call void @llvm.arm.dmb(i32 11) 178; CHECK: ret i8 [[OLDVAL]] 179 %res = atomicrmw min i8* %ptr, i8 %minend seq_cst 180 ret i8 %res 181} 182 183define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) { 184; CHECK-LABEL: @test_atomic_umax_i8 185; CHECK: call void @llvm.arm.dmb(i32 11) 186; CHECK: br label %[[LOOP:.*]] 187; CHECK: [[LOOP]]: 188; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 189; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 190; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend 191; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend 192; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 193; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 194; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 195; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 196; CHECK: [[END]]: 197; CHECK: call void @llvm.arm.dmb(i32 11) 198; CHECK: ret i8 [[OLDVAL]] 199 %res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst 200 ret i8 %res 201} 202 203define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) { 204; CHECK-LABEL: @test_atomic_umin_i8 205; CHECK: call void @llvm.arm.dmb(i32 11) 206; CHECK: br label %[[LOOP:.*]] 207; CHECK: [[LOOP]]: 208; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 209; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 210; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend 211; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend 212; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 213; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 214; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 215; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] 216; CHECK: [[END]]: 217; CHECK: call void @llvm.arm.dmb(i32 11) 218; CHECK: ret i8 [[OLDVAL]] 219 %res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst 220 ret i8 %res 221} 222 223define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) { 224; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst 225; CHECK: br label %[[START:.*]] 226 227; CHECK: [[START]]: 228; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 229; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 230; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired 231; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] 232 233; CHECK: [[FENCED_STORE]]: 234; CHECK: call void @llvm.arm.dmb(i32 11) 235; CHECK: br label %[[LOOP:.*]] 236 237; CHECK: [[LOOP]]: 238; CHECK: [[LOADED_LOOP:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] 239; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 240; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) 241; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 242; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD]] 243 244; CHECK: [[RELEASED_LOAD]]: 245; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) 246; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i8 247; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i8 [[OLDVAL_LOOP]], %desired 248; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] 249 250; CHECK: [[SUCCESS_BB]]: 251; CHECK: call void @llvm.arm.dmb(i32 11) 252; CHECK: br label %[[DONE:.*]] 253 254; CHECK: [[NO_STORE_BB]]: 255; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i8 [ [[OLDVAL]], %[[START]] ], [ [[OLDVAL_LOOP]], %[[RELEASED_LOAD]] ] 256; CHECK-NEXT: call void @llvm.arm.clrex() 257; CHECK-NEXT: br label %[[FAILURE_BB:.*]] 258 259; CHECK: [[FAILURE_BB]]: 260; CHECK: [[LOADED_FAILURE:%.*]] = phi i8 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] 261; CHECK: call void @llvm.arm.dmb(i32 11) 262; CHECK: br label %[[DONE]] 263 264; CHECK: [[DONE]]: 265; CHECK: [[LOADED:%.*]] = phi i8 [ [[LOADED_LOOP]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] 266; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] 267; CHECK: ret i8 [[LOADED]] 268 269 %pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst 270 %old = extractvalue { i8, i1 } %pairold, 0 271 ret i8 %old 272} 273 274define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) { 275; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic 276; CHECK: br label %[[LOOP:.*]] 277 278; CHECK: [[LOOP]]: 279; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) 280; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 281; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired 282; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] 283 284; CHECK: [[FENCED_STORE]]: 285; CHECK: call void @llvm.arm.dmb(i32 11) 286; CHECK: br label %[[LOOP:.*]] 287 288; CHECK: [[LOOP]]: 289; CHECK: [[LOADED_LOOP:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] 290; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 291; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) 292; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 293; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:.*]] 294 295; CHECK: [[RELEASED_LOAD]]: 296; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) 297; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i16 298; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i16 [[OLDVAL_LOOP]], %desired 299; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] 300 301; CHECK: [[SUCCESS_BB]]: 302; CHECK: call void @llvm.arm.dmb(i32 11) 303; CHECK: br label %[[DONE:.*]] 304 305; CHECK: [[NO_STORE_BB]]: 306; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i16 [ [[OLDVAL]], %[[START]] ], [ [[OLDVAL_LOOP]], %[[RELEASED_LOAD]] ] 307; CHECK-NEXT: call void @llvm.arm.clrex() 308; CHECK-NEXT: br label %[[FAILURE_BB:.*]] 309 310; CHECK: [[FAILURE_BB]]: 311; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i16 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] 312; CHECK-NOT: dmb 313; CHECK: br label %[[DONE]] 314 315; CHECK: [[DONE]]: 316; CHECK: [[LOADED:%.*]] = phi i16 [ [[LOADED_LOOP]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] 317; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] 318; CHECK: ret i16 [[LOADED]] 319 320 %pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic 321 %old = extractvalue { i16, i1 } %pairold, 0 322 ret i16 %old 323} 324 325define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) { 326; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire 327; CHECK-NOT: dmb 328; CHECK: br label %[[LOOP:.*]] 329 330; CHECK: [[LOOP]]: 331; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr) 332; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired 333; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] 334 335; CHECK: [[FENCED_STORE]]: 336; CHECK-NEXT: br label %[[TRY_STORE:.*]] 337 338; CHECK: [[TRY_STORE]]: 339; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ] 340; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr) 341; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 342; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] 343 344; CHECK: [[SUCCESS_BB]]: 345; CHECK: call void @llvm.arm.dmb(i32 11) 346; CHECK: br label %[[DONE:.*]] 347 348; CHECK: [[NO_STORE_BB]]: 349; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i32 [ [[OLDVAL]], %[[LOOP]] ] 350; CHECK-NEXT: call void @llvm.arm.clrex() 351; CHECK-NEXT: br label %[[FAILURE_BB:.*]] 352 353; CHECK: [[FAILURE_BB]]: 354; CHECK: [[LOADED_FAILURE:%.*]] = phi i32 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] 355; CHECK: call void @llvm.arm.dmb(i32 11) 356; CHECK: br label %[[DONE]] 357 358; CHECK: [[DONE]]: 359; CHECK: [[LOADED_EXIT:%.*]] = phi i32 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] 360; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] 361; CHECK: ret i32 [[LOADED_EXIT]] 362 363 %pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire 364 %old = extractvalue { i32, i1 } %pairold, 0 365 ret i32 %old 366} 367 368define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) { 369; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic 370; CHECK-NOT: dmb 371; CHECK: br label %[[LOOP:.*]] 372 373; CHECK: [[LOOP]]: 374; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* 375; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) 376; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 377; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 378; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 379; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64 380; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 381; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] 382; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired 383; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] 384 385; CHECK: [[FENCED_STORE]]: 386; CHECK-NEXT: br label %[[TRY_STORE:.*]] 387 388; CHECK: [[TRY_STORE]]: 389; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i64 [ [[OLDVAL]], %[[FENCED_STORE]] ] 390; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32 391; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32 392; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 393; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* 394; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) 395; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 396; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] 397 398; CHECK: [[SUCCESS_BB]]: 399; CHECK-NOT: dmb 400; CHECK: br label %[[DONE:.*]] 401 402; CHECK: [[NO_STORE_BB]]: 403; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i64 [ [[OLDVAL]], %[[LOOP]] ] 404; CHECK-NEXT: call void @llvm.arm.clrex() 405; CHECK-NEXT: br label %[[FAILURE_BB:.*]] 406 407; CHECK: [[FAILURE_BB]]: 408; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i64 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] 409; CHECK-NOT: dmb 410; CHECK: br label %[[DONE]] 411 412; CHECK: [[DONE]]: 413; CHECK: [[LOADED_EXIT:%.*]] = phi i64 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] 414; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] 415; CHECK: ret i64 [[LOADED_EXIT]] 416 417 %pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic 418 %old = extractvalue { i64, i1 } %pairold, 0 419 ret i64 %old 420} 421 422define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize { 423; CHECK-LABEL: @test_cmpxchg_minsize 424; CHECK: call void @llvm.arm.dmb(i32 11) 425; CHECK: br label %[[START:.*]] 426 427; CHECK: [[START]]: 428; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) 429; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired 430; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] 431 432; CHECK: [[FENCED_STORE]]: 433; CHECK-NEXT: br label %[[TRY_STORE:.*]] 434 435; CHECK: [[TRY_STORE]]: 436; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] 437; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) 438; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 439; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[START]] 440 441; CHECK: [[SUCCESS_BB]]: 442; CHECK: call void @llvm.arm.dmb(i32 11) 443; CHECK: br label %[[END:.*]] 444 445; CHECK: [[NO_STORE_BB]]: 446; CHECK: [[LOADED_NO_STORE:%.*]] = phi i32 [ [[LOADED]], %[[START]] ] 447; CHECK: call void @llvm.arm.clrex() 448; CHECK: br label %[[FAILURE_BB]] 449 450; CHECK: [[FAILURE_BB]]: 451; CHECK: [[LOADED_FAILURE:%.*]] = phi i32 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] 452; CHECK: call void @llvm.arm.dmb(i32 11) 453; CHECK: br label %[[END]] 454 455; CHECK: [[END]]: 456; CHECK: [[LOADED_EXIT:%.*]] = phi i32 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] 457; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] 458; CHECK: ret i32 [[LOADED_EXIT]] 459 460 %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst 461 %oldval = extractvalue { i32, i1 } %pair, 0 462 ret i32 %oldval 463} 464