Home
last modified time | relevance | path

Searched refs:elr_el3 (Results 1 – 24 of 24) sorted by relevance

/external/arm-trusted-firmware/bl32/tsp/
Dtsp_interrupt.c29 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) in tsp_update_sync_sel1_intr_stats() argument
40 read_mpidr(), elr_el3); in tsp_update_sync_sel1_intr_stats()
Dtsp_private.h100 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
/external/arm-trusted-firmware/services/std_svc/sdei/
Dsdei_intr_mgmt.c37 uint64_t elr_el3; member
173 disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3); in save_event_ctx()
193 write_ctx_reg(tgt_el3, CTX_ELR_EL3, disp_ctx->elr_el3); in restore_event_ctx()
256 SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3); in setup_ns_dispatch()
669 write_elr_el2(disp_ctx->elr_el3); in sdei_event_complete()
673 write_elr_el1(disp_ctx->elr_el3); in sdei_event_complete()
/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_fiq_glue.c66 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler()
139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
/external/arm-trusted-firmware/lib/cpus/aarch64/
Dwa_cve_2017_5715_bpiall.S58 mrs x7, elr_el3
85 msr elr_el3, x11
277 msr elr_el3, x7
Dneoverse_n1.S646 mrs x3, elr_el3
648 msr elr_el3, x3
/external/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
Dtegra_gic.h17 uint64_t elr_el3; member
/external/arm-trusted-firmware/bl31/aarch64/
Druntime_exceptions.S222 mrs x1, elr_el3
498 mrs x17, elr_el3
590 mrs x4, elr_el3
Dea_delegate.S246 mrs x3, elr_el3
299 msr elr_el3, x2
Dcrash_reporting.S399 mrs x15, elr_el3
/external/arm-trusted-firmware/bl1/aarch64/
Dbl1_exceptions.S182 msr elr_el3, x0
271 mrs x17, elr_el3
/external/arm-trusted-firmware/bl2/aarch64/
Dbl2_el3_entrypoint.S99 msr elr_el3, x0
/external/arm-trusted-firmware/plat/qti/qtiseclib/inc/
Dqtiseclib_defs.h77 uint64_t elr_el3; member
/external/arm-trusted-firmware/plat/hisilicon/hikey/aarch64/
Dhikey_helpers.S117 mrs x4, elr_el3
/external/arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/
Dhikey960_helpers.S121 mrs x4, elr_el3
/external/arm-trusted-firmware/plat/qti/qtiseclib/src/
Dqtiseclib_cb_interface.c138 qti_ns_ctx->elr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_ELR_EL3); in qtiseclib_cb_get_ns_ctx()
/external/arm-trusted-firmware/plat/renesas/common/aarch64/
Dplat_helpers.S190 msr elr_el3, x0
/external/arm-trusted-firmware/include/arch/aarch64/
Darch_helpers.h262 DEFINE_SYSREG_RW_FUNCS(elr_el3) in DEFINE_SYSREG_READ_FUNC()
/external/arm-trusted-firmware/lib/el3_runtime/aarch64/
Dcontext.S966 msr elr_el3, x17
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs1562 0x2c,0x40,0x1e,0xd5 = msr elr_el3, x12
1874 0x29,0x40,0x3e,0xd5 = mrs x9, elr_el3
/external/arm-trusted-firmware/docs/design/
Dinterrupt-framework-design.rst788 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
Dfirmware-design.rst1224 elr_el3 = 0x0000000088000114
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt3288 # CHECK: msr {{elr_el3|ELR_EL3}}, x12
3580 # CHECK: mrs x9, {{elr_el3|ELR_EL3}}
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt3275 # CHECK: msr {{elr_el3|ELR_EL3}}, x12
3569 # CHECK: mrs x9, {{elr_el3|ELR_EL3}}