1 /*
2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <bl32/tsp/tsp.h>
13 #include <common/debug.h>
14 #include <plat/common/platform.h>
15
16 #include "tsp_private.h"
17
18 /*******************************************************************************
19 * This function updates the TSP statistics for S-EL1 interrupts handled
20 * synchronously i.e the ones that have been handed over by the TSPD. It also
21 * keeps count of the number of times control was passed back to the TSPD
22 * after handling the interrupt. In the future it will be possible that the
23 * TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to
24 * return execution. This statistic will be useful to distinguish between these
25 * two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter
26 * contains the address of the instruction in normal world where this S-EL1
27 * interrupt was generated.
28 ******************************************************************************/
tsp_update_sync_sel1_intr_stats(uint32_t type,uint64_t elr_el3)29 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3)
30 {
31 uint32_t linear_id = plat_my_core_pos();
32
33 tsp_stats[linear_id].sync_sel1_intr_count++;
34 if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN)
35 tsp_stats[linear_id].sync_sel1_intr_ret_count++;
36
37 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
38 spin_lock(&console_lock);
39 VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%llx\n",
40 read_mpidr(), elr_el3);
41 VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
42 " %d sync s-el1 interrupt returns\n",
43 read_mpidr(),
44 tsp_stats[linear_id].sync_sel1_intr_count,
45 tsp_stats[linear_id].sync_sel1_intr_ret_count);
46 spin_unlock(&console_lock);
47 #endif
48 }
49
50 /******************************************************************************
51 * This function is invoked when a non S-EL1 interrupt is received and causes
52 * the preemption of TSP. This function returns TSP_PREEMPTED and results
53 * in the control being handed over to EL3 for handling the interrupt.
54 *****************************************************************************/
tsp_handle_preemption(void)55 int32_t tsp_handle_preemption(void)
56 {
57 uint32_t linear_id = plat_my_core_pos();
58
59 tsp_stats[linear_id].preempt_intr_count++;
60 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
61 spin_lock(&console_lock);
62 VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n",
63 read_mpidr(), tsp_stats[linear_id].preempt_intr_count);
64 spin_unlock(&console_lock);
65 #endif
66 return TSP_PREEMPTED;
67 }
68
69 /*******************************************************************************
70 * TSP interrupt handler is called as a part of both synchronous and
71 * asynchronous handling of TSP interrupts. Currently the physical timer
72 * interrupt is the only S-EL1 interrupt that this handler expects. It returns
73 * 0 upon successfully handling the expected interrupt and all other
74 * interrupts are treated as normal world or EL3 interrupts.
75 ******************************************************************************/
tsp_common_int_handler(void)76 int32_t tsp_common_int_handler(void)
77 {
78 uint32_t linear_id = plat_my_core_pos(), id;
79
80 /*
81 * Get the highest priority pending interrupt id and see if it is the
82 * secure physical generic timer interrupt in which case, handle it.
83 * Otherwise throw this interrupt at the EL3 firmware.
84 *
85 * There is a small time window between reading the highest priority
86 * pending interrupt and acknowledging it during which another
87 * interrupt of higher priority could become the highest pending
88 * interrupt. This is not expected to happen currently for TSP.
89 */
90 id = plat_ic_get_pending_interrupt_id();
91
92 /* TSP can only handle the secure physical timer interrupt */
93 if (id != TSP_IRQ_SEC_PHY_TIMER)
94 return tsp_handle_preemption();
95
96 /*
97 * Acknowledge and handle the secure timer interrupt. Also sanity check
98 * if it has been preempted by another interrupt through an assertion.
99 */
100 id = plat_ic_acknowledge_interrupt();
101 assert(id == TSP_IRQ_SEC_PHY_TIMER);
102 tsp_generic_timer_handler();
103 plat_ic_end_of_interrupt(id);
104
105 /* Update the statistics and print some messages */
106 tsp_stats[linear_id].sel1_intr_count++;
107 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
108 spin_lock(&console_lock);
109 VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
110 read_mpidr(), id);
111 VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
112 read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
113 spin_unlock(&console_lock);
114 #endif
115 return 0;
116 }
117