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Searched refs:exec_hi (Results 1 – 25 of 55) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Datomic_optimizations_global_pointer.ll13 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
15 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
19 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
31 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
33 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
37 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
71 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
73 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
77 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
90 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
[all …]
Dfold-reload-into-exec.mir39 ; CHECK: S_NOP 0, implicit-def $exec_hi
40 ; CHECK: $sgpr0 = S_MOV_B32 $exec_hi
45 ; CHECK: $exec_hi = S_MOV_B32 killed $sgpr0
47 S_NOP 0, implicit-def $exec_hi
48 %0:sreg_32 = COPY $exec_hi
50 $exec_hi = COPY %0
115 …: S_NOP 0, implicit-def renamable $sgpr0, implicit-def dead renamable $sgpr1, implicit-def $exec_hi
120 ; CHECK: $exec_hi = S_MOV_B32 killed $sgpr0
122 S_NOP 0, implicit-def %0:sreg_32, implicit-def %1:sreg_32, implicit-def $exec_hi
124 $exec_hi = COPY %0
Datomic_optimizations_raw_buffer.ll15 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
17 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
21 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
33 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
35 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
39 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
86 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
88 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
92 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
104 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
[all …]
Dread_register.ll19 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi
65 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
68 %exec_hi = call i32 @llvm.read_register.i32(metadata !6)
69 store i32 %exec_hi, i32 addrspace(1)* %out
81 !6 = !{!"exec_hi"}
Datomic_optimizations_struct_buffer.ll15 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
17 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
21 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
33 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
35 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
39 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
99 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
101 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
105 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
117 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
[all …]
Datomic_optimizations_buffer.ll16 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
18 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
22 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
34 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
36 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
40 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
118 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
120 ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
124 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
136 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
[all …]
Dwrite_register.ll82 ; CHECK: s_mov_b32 exec_hi, 0
83 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
102 !6 = !{!"exec_hi"}
/external/llvm-project/llvm/test/MC/AMDGPU/
Dsmem-err.s15 s_store_dword exec_hi, s[2:3], 0x0
27 s_buffer_store_dword exec_hi, s[0:3], 0x0
39 s_load_dword exec_hi, s[0:1], s4
51 s_buffer_load_dword exec_hi, s[0:3], s4
Dgfx9_unsupported.s61 s_and_saveexec_b32 exec_hi, s1
64 s_andn1_saveexec_b32 exec_hi, s1
67 s_andn1_wrexec_b32 exec_hi, s1
70 s_andn2_saveexec_b32 exec_hi, s1
73 s_andn2_wrexec_b32 exec_hi, s1
97 s_nand_saveexec_b32 exec_hi, s1
100 s_nor_saveexec_b32 exec_hi, s1
103 s_or_saveexec_b32 exec_hi, s1
106 s_orn1_saveexec_b32 exec_hi, s1
109 s_orn2_saveexec_b32 exec_hi, s1
[all …]
Dgfx8_unsupported.s289 s_and_saveexec_b32 exec_hi, s1
292 s_andn1_saveexec_b32 exec_hi, s1
298 s_andn1_wrexec_b32 exec_hi, s1
304 s_andn2_saveexec_b32 exec_hi, s1
307 s_andn2_wrexec_b32 exec_hi, s1
502 s_lshl1_add_u32 exec_hi, s1, s2
505 s_lshl2_add_u32 exec_hi, s1, s2
508 s_lshl3_add_u32 exec_hi, s1, s2
511 s_lshl4_add_u32 exec_hi, s1, s2
517 s_mul_hi_i32 exec_hi, s1, s2
[all …]
Dgfx7_unsupported.s295 s_and_saveexec_b32 exec_hi, s1
298 s_andn1_saveexec_b32 exec_hi, s1
304 s_andn1_wrexec_b32 exec_hi, s1
310 s_andn2_saveexec_b32 exec_hi, s1
313 s_andn2_wrexec_b32 exec_hi, s1
484 s_buffer_store_dword exec_hi, s[0:3], 0x0
538 s_lshl1_add_u32 exec_hi, s1, s2
541 s_lshl2_add_u32 exec_hi, s1, s2
544 s_lshl3_add_u32 exec_hi, s1, s2
547 s_lshl4_add_u32 exec_hi, s1, s2
[all …]
Dgfx10_asm_all.s10615 s_mov_b32 exec_hi, s1
10630 s_mov_b32 s0, exec_hi
10717 s_cmov_b32 exec_hi, s1
10732 s_cmov_b32 s0, exec_hi
10819 s_not_b32 exec_hi, s1
10834 s_not_b32 s0, exec_hi
10921 s_wqm_b32 exec_hi, s1
10936 s_wqm_b32 s0, exec_hi
11023 s_brev_b32 exec_hi, s1
11038 s_brev_b32 s0, exec_hi
[all …]
Dgfx7_asm_all.s10473 s_mov_b32 exec_hi, s1
10512 s_mov_b32 s5, exec_hi
10641 s_cmov_b32 exec_hi, s1
10680 s_cmov_b32 s5, exec_hi
10809 s_not_b32 exec_hi, s1
10848 s_not_b32 s5, exec_hi
10977 s_wqm_b32 exec_hi, s1
11016 s_wqm_b32 s5, exec_hi
11145 s_brev_b32 exec_hi, s1
11184 s_brev_b32 s5, exec_hi
[all …]
Dgfx9_asm_all.s11690 s_mov_b32 exec_hi, s1
11714 s_mov_b32 s5, exec_hi
11810 s_cmov_b32 exec_hi, s1
11834 s_cmov_b32 s5, exec_hi
11930 s_not_b32 exec_hi, s1
11954 s_not_b32 s5, exec_hi
12050 s_wqm_b32 exec_hi, s1
12074 s_wqm_b32 s5, exec_hi
12170 s_brev_b32 exec_hi, s1
12194 s_brev_b32 s5, exec_hi
[all …]
Dvop-err.s27 v_movreld_b32 v0, exec_hi
108 v_cndmask_b32 v0, exec_hi, v2, vcc
168 v_addc_u32 v0, vcc, exec_hi, v0, vcc
220 v_madak_f32 v0, exec_hi, v0, 0x11213141
Dgfx8_asm_all.s11248 s_mov_b32 exec_hi, s1
11287 s_mov_b32 s5, exec_hi
11416 s_cmov_b32 exec_hi, s1
11455 s_cmov_b32 s5, exec_hi
11584 s_not_b32 exec_hi, s1
11623 s_not_b32 s5, exec_hi
11752 s_wqm_b32 exec_hi, s1
11791 s_wqm_b32 s5, exec_hi
11920 s_brev_b32 exec_hi, s1
11959 s_brev_b32 s5, exec_hi
[all …]
Dflat-gfx9.s114 flat_load_dword v1, v[3:4], exec_hi
117 flat_store_dword v[3:4], v1, exec_hi
Dflat-gfx10.s91 flat_load_dword v1, v[3:4], exec_hi
94 flat_store_dword v[3:4], v1, exec_hi
Dflat-scratch-instructions.s244 scratch_load_dword v1, off, exec_hi
249 scratch_store_dword off, v2, exec_hi
Dreg-syntax-extra.s35 s_mov_b64 [exec_lo,exec_hi], s[2:3]
Ddl-insts.s31 v_fmac_f32 v5, exec_hi, v2
70 v_fmac_f32_e64 v5, exec_hi, v2
98 v_fmac_f32_e64 v5, v1, exec_hi
216 v_xnor_b32 v5, exec_hi, v2
255 v_xnor_b32_e64 v5, exec_hi, v2
283 v_xnor_b32_e64 v5, v1, exec_hi
316 v_xnor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
Dreg-syntax-err.s78 s_mov_b64 s[10:11], [exec_hi,exec_lo]
/external/llvm/test/CodeGen/AMDGPU/
Dread_register.ll19 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi
65 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
68 %exec_hi = call i32 @llvm.read_register.i32(metadata !6)
69 store i32 %exec_hi, i32 addrspace(1)* %out
81 !6 = !{!"exec_hi"}
Dwrite_register.ll64 ; CHECK: s_mov_b32 exec_hi, 0
65 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
80 !6 = !{!"exec_hi"}
/external/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s26 s_mov_b64 [exec_lo,exec_hi], s[2:3]

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