Home
last modified time | relevance | path

Searched refs:exec_lo (Results 1 – 25 of 87) sorted by relevance

1234

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Datomic_optimizations_global_pointer.ll12 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
13 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
14 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
18 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
19 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
30 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
31 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
32 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
36 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
37 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
[all …]
Dsgpr-spill.mir14 # CHECK: $sgpr12 = S_MOV_B32 $exec_lo
15 # CHECK: $exec_lo = S_MOV_B32 1
18 # CHECK: $exec_lo = S_MOV_B32 killed $sgpr12
22 # CHECK: $sgpr12 = S_MOV_B32 $exec_lo
23 # CHECK: $exec_lo = S_MOV_B32 1
31 # GCN32: $sgpr12 = S_MOV_B32 $exec_lo
33 # GCN32: $exec_lo = S_MOV_B32 3
37 # GCN32: $exec_lo = S_MOV_B32 killed $sgpr12
43 # GCN32: $sgpr12 = S_MOV_B32 $exec_lo
45 # GCN32: $exec_lo = S_MOV_B32 3
[all …]
Doptimize-negated-cond-exec-masking-wave32.mir5 # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
14 $vcc_lo = S_AND_B32 $exec_lo, killed $vcc_lo, implicit-def dead $scc
27 # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
36 $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
52 # GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
62 $vcc_lo = S_AND_B32 $exec_lo, killed $vcc_lo, implicit-def dead $scc
78 # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
88 $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
100 # GCN: $vcc_lo = S_AND_B32 $exec_lo, undef $vcc_lo, implicit-def dead $scc
106 $vcc_lo = S_AND_B32 $exec_lo, undef $vcc_lo, implicit-def dead $scc
[all …]
Dvcmpx-exec-war-hazard.mir4 # GCN: $sgpr0 = S_MOV_B32 $exec_lo
13 $sgpr0 = S_MOV_B32 $exec_lo
40 # GCN: $vgpr0 = V_MOV_B32_e32 $exec_lo, implicit $exec
47 $vgpr0 = V_MOV_B32_e32 $exec_lo, implicit $exec
72 # GCN: $sgpr0 = S_MOV_B32 $exec_lo
81 $sgpr0 = S_MOV_B32 $exec_lo
91 # GCN: $sgpr0 = S_MOV_B32 $exec_lo
100 $sgpr0 = S_MOV_B32 $exec_lo
110 # GCN: $sgpr0 = S_MOV_B32 $exec_lo
119 $sgpr0 = S_MOV_B32 $exec_lo
[all …]
Datomic_optimizations_raw_buffer.ll14 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
15 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
16 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
20 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
21 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
32 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
33 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
34 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
38 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
39 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
[all …]
Datomic_optimizations_struct_buffer.ll14 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
15 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
16 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
20 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
21 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
32 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
33 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
34 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
38 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
39 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
[all …]
Dllvm.amdgcn.image.gather4.a16.dim.ll19 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
20 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
23 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
46 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
47 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
50 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
73 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
74 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
77 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
100 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
[all …]
Datomic_optimizations_buffer.ll15 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
16 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
17 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
21 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
22 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
33 ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
34 ; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec
35 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
39 ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
40 ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}}
[all …]
Dllvm.amdgcn.image.sample.dim.ll27 ; GFX10-NEXT: s_mov_b32 s12, exec_lo ; encoding: [0x7e,0x03,0x8c,0xbe]
28 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo ; encoding: [0x7e,0x09,0xfe,0xbe]
29 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; encoding: [0x7e,0x0c,0x7e,0x87]
82 ; GFX10-NEXT: s_mov_b32 s28, exec_lo ; encoding: [0x7e,0x03,0x9c,0xbe]
83 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo ; encoding: [0x7e,0x09,0xfe,0xbe]
95 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s28 ; encoding: [0x7e,0x1c,0x7e,0x87]
136 ; GFX10-NEXT: s_mov_b32 s12, exec_lo ; encoding: [0x7e,0x03,0x8c,0xbe]
137 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo ; encoding: [0x7e,0x09,0xfe,0xbe]
141 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; encoding: [0x7e,0x0c,0x7e,0x87]
183 ; GFX10-NEXT: s_mov_b32 s12, exec_lo ; encoding: [0x7e,0x03,0x8c,0xbe]
[all …]
Dllvm.amdgcn.image.sample.a16.dim.ll17 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
18 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
19 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
42 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
43 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
46 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
69 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
70 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
73 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
96 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
[all …]
Dfold-reload-into-exec.mir15 ; CHECK: S_NOP 0, implicit-def $exec_lo
16 ; CHECK: $sgpr0 = S_MOV_B32 $exec_lo
21 ; CHECK: $exec_lo = S_MOV_B32 killed $sgpr0
23 S_NOP 0, implicit-def $exec_lo
24 %0:sreg_32 = COPY $exec_lo
26 $exec_lo = COPY %0
93 …: S_NOP 0, implicit-def renamable $sgpr0, implicit-def dead renamable $sgpr1, implicit-def $exec_lo
98 ; CHECK: $exec_lo = S_MOV_B32 killed $sgpr0
100 S_NOP 0, implicit-def %0:sreg_32, implicit-def %1:sreg_32, implicit-def $exec_lo
102 $exec_lo = COPY %0
Dread_register.ll18 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo
56 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
59 %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
60 store i32 %exec_lo, i32 addrspace(1)* %out
80 !5 = !{!"exec_lo"}
Dllvm.amdgcn.image.sample.d16.dim.ll37 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
38 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
39 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
99 ; GFX10-NEXT: s_mov_b32 s28, exec_lo
100 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
105 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s28
238 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
239 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
240 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
301 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
[all …]
Dmubuf-legalize-operands.ll27 ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
39 ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
41 ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
92 ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
104 ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
107 ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
109 ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
122 ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
125 ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
188 ; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
[all …]
Datomic_optimizations_pixelshader.ll150 ; GFX1032-NEXT: s_mov_b32 s9, exec_lo
155 ; GFX1032-NEXT: s_mov_b32 s10, exec_lo
167 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s9
172 ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s8
174 ; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4
218 ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
273 ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
345 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
381 ; GFX1032-NEXT: s_mov_b32 s9, exec_lo
387 ; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo
[all …]
Dvgpr-descriptor-waterfall-loop-idom-update.ll13 ; GCN-NEXT: s_mov_b32 s5, exec_lo
32 ; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s4
35 ; GCN-NEXT: s_mov_b32 exec_lo, s5
Dwave32.ll170 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}}
180 ; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}}
184 ; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}}
237 ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo
239 ; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo
244 ; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]]
248 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]]
253 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], exec_lo
448 ; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE]]
496 ; GFX1032: s_and_b32 vcc_lo, exec_lo, vcc_lo
[all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dreg-syntax-err.s75 s_mov_b64 s[10:11], [exec_lo,vcc_hi]
78 s_mov_b64 s[10:11], [exec_hi,exec_lo]
81 s_mov_b64 s[10:11], [exec_lo,exec_lo]
84 s_mov_b64 s[10:11], [exec,exec_lo]
87 s_mov_b64 s[10:11], [exec_lo,exec]
90 s_mov_b64 s[10:11], [exec_lo,s0]
93 s_mov_b64 s[10:11], [s0,exec_lo]
Dsmem-err.s12 s_store_dword exec_lo, s[2:3], 0x0
24 s_buffer_store_dword exec_lo, s[0:3], 0x0
36 s_load_dword exec_lo, s[0:1], s4
48 s_buffer_load_dword exec_lo, s[0:3], s4
Dgfx10_asm_all.s10612 s_mov_b32 exec_lo, s1
10627 s_mov_b32 s0, exec_lo
10714 s_cmov_b32 exec_lo, s1
10729 s_cmov_b32 s0, exec_lo
10816 s_not_b32 exec_lo, s1
10831 s_not_b32 s0, exec_lo
10918 s_wqm_b32 exec_lo, s1
10933 s_wqm_b32 s0, exec_lo
11020 s_brev_b32 exec_lo, s1
11035 s_brev_b32 s0, exec_lo
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.image.gather4.dim.ll29 ; GFX10NSA-NEXT: s_mov_b32 s1, exec_lo
31 ; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
32 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s1
76 ; GFX10NSA-NEXT: s_mov_b32 s1, exec_lo
78 ; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
79 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s1
123 ; GFX10NSA-NEXT: s_mov_b32 s1, exec_lo
125 ; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
126 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s1
170 ; GFX10NSA-NEXT: s_mov_b32 s1, exec_lo
[all …]
Dllvm.amdgcn.image.gather4.a16.dim.ll32 ; GFX10NSA-NEXT: s_mov_b32 s28, exec_lo
34 ; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
48 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s28
86 ; GFX10NSA-NEXT: s_mov_b32 s28, exec_lo
88 ; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
105 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s28
143 ; GFX10NSA-NEXT: s_mov_b32 s28, exec_lo
145 ; GFX10NSA-NEXT: s_wqm_b32 exec_lo, exec_lo
162 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s28
198 ; GFX10NSA-NEXT: s_mov_b32 s28, exec_lo
[all …]
Dllvm.amdgcn.image.gather4.o.dim.ll29 ; GFX10-NEXT: s_mov_b32 s1, exec_lo
31 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
32 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s1
76 ; GFX10-NEXT: s_mov_b32 s1, exec_lo
78 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
79 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s1
123 ; GFX10-NEXT: s_mov_b32 s1, exec_lo
125 ; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
126 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s1
170 ; GFX10-NEXT: s_mov_b32 s1, exec_lo
[all …]
Dllvm.amdgcn.intersect_ray.ll81 ; GCN-NEXT: s_mov_b32 s1, exec_lo
93 ; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s0
96 ; GCN-NEXT: s_mov_b32 exec_lo, s1
116 ; GCN-NEXT: s_mov_b32 s1, exec_lo
133 ; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s0
136 ; GCN-NEXT: s_mov_b32 exec_lo, s1
151 ; GCN-NEXT: s_mov_b32 s1, exec_lo
163 ; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s0
166 ; GCN-NEXT: s_mov_b32 exec_lo, s1
186 ; GCN-NEXT: s_mov_b32 s1, exec_lo
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dread_register.ll18 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo
56 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
59 %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
60 store i32 %exec_lo, i32 addrspace(1)* %out
80 !5 = !{!"exec_lo"}

1234