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Searched refs:fcsel (Results 1 – 25 of 64) sorted by relevance

123

/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfcsel-zero.ll11 ; CHECK-NEXT: fcsel {{s[0-9]+}}, [[R]], {{s[0-9]+}}, eq
20 ; CHECK-NEXT: fcsel {{s[0-9]+}}, [[R]], {{s[0-9]+}}, eq
21 ; CHECK-NEXT: fcsel {{s[0-9]+}}, [[R]], {{s[0-9]+}}, vs
30 ; CHECK-NEXT: fcsel {{s[0-9]+}}, {{s[0-9]+}}, [[R]], mi
31 ; CHECK-NEXT: fcsel {{s[0-9]+}}, {{s[0-9]+}}, [[R]], gt
40 ; CHECK-NEXT: fcsel {{s[0-9]+}}, {{s[0-9]+}}, [[R]], ne
49 ; CHECK-NEXT: fcsel {{d[0-9]+}}, [[R]], {{d[0-9]+}}, eq
58 ; CHECK-NEXT: fcsel {{d[0-9]+}}, [[R]], {{d[0-9]+}}, eq
59 ; CHECK-NEXT: fcsel {{d[0-9]+}}, [[R]], {{d[0-9]+}}, vs
68 ; CHECK-NEXT: fcsel {{d[0-9]+}}, {{d[0-9]+}}, [[R]], mi
[all …]
Dfast-isel-select.ll49 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
52 ; GISEL-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
60 ; CHECK-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne
63 ; GISEL-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne
80 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, gt
89 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ge
98 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, mi
107 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ls
116 ; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, mi
117 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], gt
[all …]
Darm64-fcmp-opt.ll46 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq
58 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt
70 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge
82 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi
94 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls
106 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc
117 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs
128 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi
139 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl
150 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt
[all …]
Ddirectcond.ll26 ; CHECK-NEXT: fcsel s0, s0, s1, ne
27 ; CHECK-NOFP-NOT: fcsel
35 ; CHECK-NEXT: fcsel d0, d0, d1, ne
36 ; CHECK-NOFP-NOT: fcsel
Darm64-fmax.ll36 ; results. Make sure they're put back before we resort to the normal fcsel.
45 ; CHECK: fcsel s0, s1, s0, ne
63 ; CHECK: fcsel
Dfp-cond-sel.ll17 ; CHECK: fcsel {{s[0-9]+}}, s[[FLT0]], s[[FLT1]], hi
25 ; CHECK: fcsel {{d[0-9]+}}, d[[FLT1]], d[[FLT0]], le
Dregress-f128csel-flags.ll20 ; It's also reasonably important that the actual fcsel comes before the
23 ; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne
Darm64-regress-f128csel-flags.ll20 ; It's also reasonably important that the actual fcsel comes before the
23 ; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne
Darm64-fmax-safe.ll36 ; results. Make sure they're put back before we resort to the normal fcsel.
45 ; CHECK: fcsel s0, s1, s0, ne
Dknown-never-nan.ll15 ; CHECK-NEXT: fcsel s0, s0, s1, pl
39 ; CHECK-NEXT: fcsel s0, s0, s1, pl
Dfabs.ll12 ; CHECK-NEXT: fcsel d0, d1, d0, le
29 ; CHECK-NEXT: fcsel s0, s0, s1, ge
/external/llvm/test/CodeGen/AArch64/
Dfast-isel-select.ll48 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
56 ; CHECK-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne
73 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, gt
82 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ge
91 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, mi
100 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ls
109 ; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, mi
110 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], gt
119 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vc
128 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vs
[all …]
Darm64-fcmp-opt.ll46 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq
58 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt
70 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge
82 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi
94 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls
106 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc
117 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs
128 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi
139 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl
150 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt
[all …]
Ddirectcond.ll26 ; CHECK-NEXT: fcsel s0, s0, s1, ne
27 ; CHECK-NOFP-NOT: fcsel
35 ; CHECK-NEXT: fcsel d0, d0, d1, ne
36 ; CHECK-NOFP-NOT: fcsel
Darm64-fmax.ll36 ; results. Make sure they're put back before we resort to the normal fcsel.
45 ; CHECK: fcsel s0, s1, s0, ne
63 ; CHECK: fcsel
Dfp-cond-sel.ll17 ; CHECK: fcsel {{s[0-9]+}}, s[[FLT0]], s[[FLT1]], hi
25 ; CHECK: fcsel {{d[0-9]+}}, d[[FLT1]], d[[FLT0]], le
Dregress-f128csel-flags.ll20 ; It's also reasonably important that the actual fcsel comes before the
23 ; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne
Darm64-regress-f128csel-flags.ll20 ; It's also reasonably important that the actual fcsel comes before the
23 ; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne
Darm64-fmax-safe.ll36 ; results. Make sure they're put back before we resort to the normal fcsel.
45 ; CHECK: fcsel s0, s1, s0, ne
Darm64-fp.ll5 ; CHECK: fcsel s0, s0, s1, ne
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
Dfloat-sqrt.s18 fcsel s0, s0, s1, eq label
71 # M3-NEXT: 2 5 1.00 fcsel s0, s0, s1, eq
72 # M4-NEXT: 2 5 1.00 fcsel s0, s0, s1, eq
73 # M5-NEXT: 2 2 1.00 fcsel s0, s0, s1, eq
Ddouble-sqrt.s21 fcsel d0, d0, d1, eq define
77 # M3-NEXT: 2 5 1.00 fcsel d0, d0, d1, eq
78 # M4-NEXT: 2 5 1.00 fcsel d0, d0, d1, eq
79 # M5-NEXT: 2 2 1.00 fcsel d0, d0, d1, eq
/external/vixl/test/aarch64/
Dtest-disasm-fp-aarch64.cc256 COMPARE(fcsel(h0, h1, h2, eq), "fcsel h0, h1, h2, eq"); in TEST()
257 COMPARE(fcsel(h31, h31, h30, ne), "fcsel h31, h31, h30, ne"); in TEST()
258 COMPARE(fcsel(s0, s1, s2, eq), "fcsel s0, s1, s2, eq"); in TEST()
259 COMPARE(fcsel(s31, s31, s30, ne), "fcsel s31, s31, s30, ne"); in TEST()
260 COMPARE(fcsel(d0, d1, d2, mi), "fcsel d0, d1, d2, mi"); in TEST()
261 COMPARE(fcsel(d31, d30, d31, pl), "fcsel d31, d30, d31, pl"); in TEST()
262 COMPARE(fcsel(h11, h12, h13, al), "fcsel h11, h12, h13, al"); in TEST()
263 COMPARE(fcsel(s14, s15, s16, al), "fcsel s14, s15, s16, al"); in TEST()
264 COMPARE(fcsel(d17, d18, d19, nv), "fcsel d17, d18, d19, nv"); in TEST()
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-nv-cond.s3 fcsel d28,d31,d31,nv label
/external/llvm/test/MC/AArch64/
Darm64-nv-cond.s3 fcsel d28,d31,d31,nv label

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