1; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mtriple=aarch64-apple-darwin -global-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GISEL 4 5; First test the different supported value types for select. 6define zeroext i1 @select_i1(i1 zeroext %c, i1 zeroext %a, i1 zeroext %b) { 7; CHECK-LABEL: select_i1 8; CHECK: {{cmp w0, #0|tst w0, #0x1}} 9; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne 10 %1 = select i1 %c, i1 %a, i1 %b 11 ret i1 %1 12} 13 14define zeroext i8 @select_i8(i1 zeroext %c, i8 zeroext %a, i8 zeroext %b) { 15; CHECK-LABEL: select_i8 16; CHECK: {{cmp w0, #0|tst w0, #0x1}} 17; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne 18 %1 = select i1 %c, i8 %a, i8 %b 19 ret i8 %1 20} 21 22define zeroext i16 @select_i16(i1 zeroext %c, i16 zeroext %a, i16 zeroext %b) { 23; CHECK-LABEL: select_i16 24; CHECK: {{cmp w0, #0|tst w0, #0x1}} 25; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne 26 %1 = select i1 %c, i16 %a, i16 %b 27 ret i16 %1 28} 29 30define i32 @select_i32(i1 zeroext %c, i32 %a, i32 %b) { 31; CHECK-LABEL: select_i32 32; CHECK: {{cmp w0, #0|tst w0, #0x1}} 33; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne 34 %1 = select i1 %c, i32 %a, i32 %b 35 ret i32 %1 36} 37 38define i64 @select_i64(i1 zeroext %c, i64 %a, i64 %b) { 39; CHECK-LABEL: select_i64 40; CHECK: {{cmp w0, #0|tst w0, #0x1}} 41; CHECK-NEXT: csel {{x[0-9]+}}, x1, x2, ne 42 %1 = select i1 %c, i64 %a, i64 %b 43 ret i64 %1 44} 45 46define float @select_f32(i1 zeroext %c, float %a, float %b) { 47; CHECK-LABEL: select_f32 48; CHECK: {{cmp w0, #0|tst w0, #0x1}} 49; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne 50; GISEL-LABEL: select_f32 51; GISEL: {{cmp w0, #0|tst w0, #0x1}} 52; GISEL-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne 53 %1 = select i1 %c, float %a, float %b 54 ret float %1 55} 56 57define double @select_f64(i1 zeroext %c, double %a, double %b) { 58; CHECK-LABEL: select_f64 59; CHECK: {{cmp w0, #0|tst w0, #0x1}} 60; CHECK-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne 61; GISEL-LABEL: select_f64 62; GISEL: {{cmp w0, #0|tst w0, #0x1}} 63; GISEL-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne 64 %1 = select i1 %c, double %a, double %b 65 ret double %1 66} 67 68; Now test the folding of all compares. 69define float @select_fcmp_false(float %x, float %a, float %b) { 70; CHECK-LABEL: select_fcmp_false 71; CHECK: mov.16b {{v[0-9]+}}, v2 72 %1 = fcmp ogt float %x, %x 73 %2 = select i1 %1, float %a, float %b 74 ret float %2 75} 76 77define float @select_fcmp_ogt(float %x, float %y, float %a, float %b) { 78; CHECK-LABEL: select_fcmp_ogt 79; CHECK: fcmp s0, s1 80; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, gt 81 %1 = fcmp ogt float %x, %y 82 %2 = select i1 %1, float %a, float %b 83 ret float %2 84} 85 86define float @select_fcmp_oge(float %x, float %y, float %a, float %b) { 87; CHECK-LABEL: select_fcmp_oge 88; CHECK: fcmp s0, s1 89; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ge 90 %1 = fcmp oge float %x, %y 91 %2 = select i1 %1, float %a, float %b 92 ret float %2 93} 94 95define float @select_fcmp_olt(float %x, float %y, float %a, float %b) { 96; CHECK-LABEL: select_fcmp_olt 97; CHECK: fcmp s0, s1 98; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, mi 99 %1 = fcmp olt float %x, %y 100 %2 = select i1 %1, float %a, float %b 101 ret float %2 102} 103 104define float @select_fcmp_ole(float %x, float %y, float %a, float %b) { 105; CHECK-LABEL: select_fcmp_ole 106; CHECK: fcmp s0, s1 107; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ls 108 %1 = fcmp ole float %x, %y 109 %2 = select i1 %1, float %a, float %b 110 ret float %2 111} 112 113define float @select_fcmp_one(float %x, float %y, float %a, float %b) { 114; CHECK-LABEL: select_fcmp_one 115; CHECK: fcmp s0, s1 116; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, mi 117; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], gt 118 %1 = fcmp one float %x, %y 119 %2 = select i1 %1, float %a, float %b 120 ret float %2 121} 122 123define float @select_fcmp_ord(float %x, float %y, float %a, float %b) { 124; CHECK-LABEL: select_fcmp_ord 125; CHECK: fcmp s0, s1 126; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vc 127 %1 = fcmp ord float %x, %y 128 %2 = select i1 %1, float %a, float %b 129 ret float %2 130} 131 132define float @select_fcmp_uno(float %x, float %y, float %a, float %b) { 133; CHECK-LABEL: select_fcmp_uno 134; CHECK: fcmp s0, s1 135; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vs 136 %1 = fcmp uno float %x, %y 137 %2 = select i1 %1, float %a, float %b 138 ret float %2 139} 140 141define float @select_fcmp_ueq(float %x, float %y, float %a, float %b) { 142; CHECK-LABEL: select_fcmp_ueq 143; CHECK: fcmp s0, s1 144; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, eq 145; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], vs 146 %1 = fcmp ueq float %x, %y 147 %2 = select i1 %1, float %a, float %b 148 ret float %2 149} 150 151define float @select_fcmp_ugt(float %x, float %y, float %a, float %b) { 152; CHECK-LABEL: select_fcmp_ugt 153; CHECK: fcmp s0, s1 154; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, hi 155 %1 = fcmp ugt float %x, %y 156 %2 = select i1 %1, float %a, float %b 157 ret float %2 158} 159 160define float @select_fcmp_uge(float %x, float %y, float %a, float %b) { 161; CHECK-LABEL: select_fcmp_uge 162; CHECK: fcmp s0, s1 163; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, pl 164 %1 = fcmp uge float %x, %y 165 %2 = select i1 %1, float %a, float %b 166 ret float %2 167} 168 169define float @select_fcmp_ult(float %x, float %y, float %a, float %b) { 170; CHECK-LABEL: select_fcmp_ult 171; CHECK: fcmp s0, s1 172; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, lt 173 %1 = fcmp ult float %x, %y 174 %2 = select i1 %1, float %a, float %b 175 ret float %2 176} 177 178 179define float @select_fcmp_ule(float %x, float %y, float %a, float %b) { 180; CHECK-LABEL: select_fcmp_ule 181; CHECK: fcmp s0, s1 182; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, le 183 %1 = fcmp ule float %x, %y 184 %2 = select i1 %1, float %a, float %b 185 ret float %2 186} 187 188define float @select_fcmp_une(float %x, float %y, float %a, float %b) { 189; CHECK-LABEL: select_fcmp_une 190; CHECK: fcmp s0, s1 191; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ne 192 %1 = fcmp une float %x, %y 193 %2 = select i1 %1, float %a, float %b 194 ret float %2 195} 196 197define float @select_fcmp_true(float %x, float %a, float %b) { 198; CHECK-LABEL: select_fcmp_true 199; CHECK: mov.16b {{v[0-9]+}}, v1 200 %1 = fcmp ueq float %x, %x 201 %2 = select i1 %1, float %a, float %b 202 ret float %2 203} 204 205define float @select_icmp_eq(i32 %x, i32 %y, float %a, float %b) { 206; CHECK-LABEL: select_icmp_eq 207; CHECK: cmp w0, w1 208; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, eq 209 %1 = icmp eq i32 %x, %y 210 %2 = select i1 %1, float %a, float %b 211 ret float %2 212} 213 214define float @select_icmp_ne(i32 %x, i32 %y, float %a, float %b) { 215; CHECK-LABEL: select_icmp_ne 216; CHECK: cmp w0, w1 217; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne 218 %1 = icmp ne i32 %x, %y 219 %2 = select i1 %1, float %a, float %b 220 ret float %2 221} 222 223define float @select_icmp_ugt(i32 %x, i32 %y, float %a, float %b) { 224; CHECK-LABEL: select_icmp_ugt 225; CHECK: cmp w0, w1 226; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, hi 227 %1 = icmp ugt i32 %x, %y 228 %2 = select i1 %1, float %a, float %b 229 ret float %2 230} 231 232define float @select_icmp_uge(i32 %x, i32 %y, float %a, float %b) { 233; CHECK-LABEL: select_icmp_uge 234; CHECK: cmp w0, w1 235; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, hs 236 %1 = icmp uge i32 %x, %y 237 %2 = select i1 %1, float %a, float %b 238 ret float %2 239} 240 241define float @select_icmp_ult(i32 %x, i32 %y, float %a, float %b) { 242; CHECK-LABEL: select_icmp_ult 243; CHECK: cmp w0, w1 244; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, lo 245 %1 = icmp ult i32 %x, %y 246 %2 = select i1 %1, float %a, float %b 247 ret float %2 248} 249 250define float @select_icmp_ule(i32 %x, i32 %y, float %a, float %b) { 251; CHECK-LABEL: select_icmp_ule 252; CHECK: cmp w0, w1 253; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ls 254 %1 = icmp ule i32 %x, %y 255 %2 = select i1 %1, float %a, float %b 256 ret float %2 257} 258 259define float @select_icmp_sgt(i32 %x, i32 %y, float %a, float %b) { 260; CHECK-LABEL: select_icmp_sgt 261; CHECK: cmp w0, w1 262; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, gt 263 %1 = icmp sgt i32 %x, %y 264 %2 = select i1 %1, float %a, float %b 265 ret float %2 266} 267 268define float @select_icmp_sge(i32 %x, i32 %y, float %a, float %b) { 269; CHECK-LABEL: select_icmp_sge 270; CHECK: cmp w0, w1 271; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ge 272 %1 = icmp sge i32 %x, %y 273 %2 = select i1 %1, float %a, float %b 274 ret float %2 275} 276 277define float @select_icmp_slt(i32 %x, i32 %y, float %a, float %b) { 278; CHECK-LABEL: select_icmp_slt 279; CHECK: cmp w0, w1 280; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, lt 281 %1 = icmp slt i32 %x, %y 282 %2 = select i1 %1, float %a, float %b 283 ret float %2 284} 285 286define float @select_icmp_sle(i32 %x, i32 %y, float %a, float %b) { 287; CHECK-LABEL: select_icmp_sle 288; CHECK: cmp w0, w1 289; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, le 290 %1 = icmp sle i32 %x, %y 291 %2 = select i1 %1, float %a, float %b 292 ret float %2 293} 294 295; Test peephole optimizations for select. 296define zeroext i1 @select_opt1(i1 zeroext %c, i1 zeroext %a) { 297; CHECK-LABEL: select_opt1 298; CHECK: orr {{w[0-9]+}}, w0, w1 299 %1 = select i1 %c, i1 true, i1 %a 300 ret i1 %1 301} 302 303define zeroext i1 @select_opt2(i1 zeroext %c, i1 zeroext %a) { 304; CHECK-LABEL: select_opt2 305; CHECK: eor [[REG:w[0-9]+]], w0, #0x1 306; CHECK: orr {{w[0-9]+}}, [[REG]], w1 307 %1 = select i1 %c, i1 %a, i1 true 308 ret i1 %1 309} 310 311define zeroext i1 @select_opt3(i1 zeroext %c, i1 zeroext %a) { 312; CHECK-LABEL: select_opt3 313; CHECK: bic {{w[0-9]+}}, w1, w0 314 %1 = select i1 %c, i1 false, i1 %a 315 ret i1 %1 316} 317 318define zeroext i1 @select_opt4(i1 zeroext %c, i1 zeroext %a) { 319; CHECK-LABEL: select_opt4 320; CHECK: and {{w[0-9]+}}, w0, w1 321 %1 = select i1 %c, i1 %a, i1 false 322 ret i1 %1 323} 324