| /external/mesa3d/src/mesa/sparc/ |
| D | norm.S | 60 fmuls %f0, M0, %f3 ! FGM Group
61 fmuls %f1, M1, %f4 ! FGM Group
62 fmuls %f0, M4, %f5 ! FGM Group
63 fmuls %f1, M5, %f6 ! FGM Group
64 fmuls %f0, M8, %f7 ! FGM Group f3 available
65 fmuls %f1, M9, %f8 ! FGM Group f4 available
67 fmuls %f2, M2, %f10 ! FGM Group f5 available
68 fmuls %f2, M6, %f0 ! FGM Group f6 available
70 fmuls %f2, M10, %f4 ! FGM Group f7 available
79 fmuls %f3, %f3, %f6 ! FGM Group f3 available
[all …]
|
| D | xform.S | 82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
83 fmuls %f0, M1, %f2 ! FGM Group
84 fmuls %f0, M2, %f3 ! FGM Group
85 fmuls %f0, M3, %f4 ! FGM Group
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
89 fmuls %f8, M1, %f10 ! FGM Group f2 available
92 fmuls %f8, M2, %f11 ! FGM Group f3 available
95 fmuls %f8, M3, %f12 ! FGM Group f4 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
116 fmuls %f0, M1, %f2 ! FGM Group
[all …]
|
| D | sparc_clip.S | 135 fmuls %f0, %f8, %f0 ! FGM
137 fmuls %f1, %f8, %f1 ! FGM
139 fmuls %f2, %f8, %f2 ! FGM
|
| /external/llvm-project/llvm/test/MC/AVR/ |
| D | inst-fmuls.s | 7 fmuls r22, r16
8 fmuls r19, r17
9 fmuls r21, r23
10 fmuls r23, r23
12 ; CHECK: fmuls r22, r16 ; encoding: [0xe0,0x03]
13 ; CHECK: fmuls r19, r17 ; encoding: [0xb1,0x03]
14 ; CHECK: fmuls r21, r23 ; encoding: [0xd7,0x03]
15 ; CHECK: fmuls r23, r23 ; encoding: [0xf7,0x03]
17 ; CHECK-INST: fmuls r22, r16
18 ; CHECK-INST: fmuls r19, r17
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | recipest.ll | 50 ; CHECK: fmuls
52 ; CHECK-NEXT: fmuls
78 ; CHECK-NEXT: fmuls
95 ; CHECK: fmuls
97 ; CHECK-NEXT: fmuls
98 ; CHECK-NEXT: fmuls
104 ; CHECK-NONR: fmuls
126 ; CHECK-DAG: fmuls
130 ; CHECK: fmuls
131 ; CHECK-NEXT: fmuls
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/SPARC/ |
| D | disable-fsmuld-fmuls.ll | 2 ; RUN: llc %s -march=sparc -mattr=no-fmuls -o - | FileCheck --check-prefix=CHECK --check-prefix=NO-…
4 ; RUN: llc %s -march=sparc -mattr=no-fsmuld,no-fmuls -o - | FileCheck --check-prefix=CHECK --check-…
6 ;;; Test case ensures that the no-fsmuld and no-fmuls features disable
11 ; DEFAULT: fmuls
12 ; NO-FSMULD: fmuls
|
| D | LeonItinerariesUT.ll | 13 ; NO_ITIN-NEXT: fmuls
24 ; LEON2_ITIN-NEXT: fmuls
35 ; LEON3_4_ITIN-NEXT: fmuls
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | limited-prec.ll | 11 ; precision6-NEXT: fmuls {{\.LCPI.*}}
23 ; precision6-NEXT: fmuls {{\.LCPI.*}}
39 ; precision12-NEXT: fmuls {{\.LCPI.*}}
51 ; precision12-NEXT: fmuls {{\.LCPI.*}}
69 ; precision18-NEXT: fmuls {{\.LCPI.*}}
81 ; precision18-NEXT: fmuls {{\.LCPI.*}}
125 ; precision6-NEXT: fmuls {{\.LCPI.*}}
152 ; precision12-NEXT: fmuls {{\.LCPI.*}}
181 ; precision18-NEXT: fmuls {{\.LCPI.*}}
214 ; precision6-NEXT: fmuls {{\.LCPI.*}}
[all …]
|
| D | fmf-flags.ll | 41 ; X86-NEXT: fmuls {{\.LCPI.*}}
130 ; X86-NEXT: fmuls {{\.LCPI.*}}
|
| D | pr34080-2.ll | 52 ; CHECK-NEXT: fmuls {{\.LCPI.*}}
65 ; CHECK-NEXT: fmuls {{\.LCPI.*}}
|
| /external/llvm/test/CodeGen/SPARC/ |
| D | LeonItinerariesUT.ll | 13 ; NO_ITIN-NEXT: fmuls
24 ; LEON2_ITIN-NEXT: fmuls
35 ; LEON3_4_ITIN-NEXT: fmuls
|
| D | LeonReplaceFMULSPassUT.ll | 16 …%mul = tail call double asm sideeffect "fmuls $0, $1, $2", "={f20},{f21},{f8}"(float* %a, float* %…
|
| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-fp.s.cs | 41 0xec,0x43,0x01,0x32 = fmuls 2, 3, 4
42 0xec,0x43,0x01,0x33 = fmuls. 2, 3, 4
|
| /external/llvm-project/llvm/test/MC/X86/ |
| D | X87-64.s | 1128 fmuls 485498096 label
1132 fmuls 64(%rdx) label
1136 fmuls -64(%rdx,%rax,4) label
1140 fmuls 64(%rdx,%rax,4) label
1144 fmuls 64(%rdx,%rax) label
1148 fmuls (%rdx) label
|
| D | X87-32.s | 1128 fmuls -485498096(%edx,%eax,4) label
1132 fmuls 485498096(%edx,%eax,4) label
1136 fmuls 485498096(%edx) label
1140 fmuls 485498096 label
1144 fmuls 64(%edx,%eax) label
1148 fmuls (%edx) label
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-fp.s | 136 # CHECK-BE: fmuls 2, 3, 4 # encoding: [0xec,0x43,0x01,0x32]
137 # CHECK-LE: fmuls 2, 3, 4 # encoding: [0x32,0x01,0x43,0xec]
138 fmuls 2, 3, 4
139 # CHECK-BE: fmuls. 2, 3, 4 # encoding: [0xec,0x43,0x01,0x33]
140 # CHECK-LE: fmuls. 2, 3, 4 # encoding: [0x33,0x01,0x43,0xec]
141 fmuls. 2, 3, 4
|
| /external/llvm/test/CodeGen/NVPTX/ |
| D | machine-sink.ll | 10 ; backend would sink the fmuls to BB %merge, but not the loads for being
12 ; the two fmuls would be separated to two basic blocks, causing two
|
| /external/llvm-project/llvm/test/CodeGen/NVPTX/ |
| D | machine-sink.ll | 10 ; backend would sink the fmuls to BB %merge, but not the loads for being
12 ; the two fmuls would be separated to two basic blocks, causing two
|
| /external/llvm-project/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-fp.s | 136 # CHECK-BE: fmuls 2, 3, 4 # encoding: [0xec,0x43,0x01,0x32]
137 # CHECK-LE: fmuls 2, 3, 4 # encoding: [0x32,0x01,0x43,0xec]
138 fmuls 2, 3, 4
139 # CHECK-BE: fmuls. 2, 3, 4 # encoding: [0xec,0x43,0x01,0x33]
140 # CHECK-LE: fmuls. 2, 3, 4 # encoding: [0x33,0x01,0x43,0xec]
141 fmuls. 2, 3, 4
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | recipest.ll | 129 ; CHECK-P7-NEXT: fmuls 2, 2, 0
131 ; CHECK-P7-NEXT: fmuls 0, 0, 4
132 ; CHECK-P7-NEXT: fmuls 0, 0, 2
210 ; CHECK-P7-NEXT: fmuls 1, 1, 0
293 ; CHECK-P7-NEXT: fmuls 2, 2, 0
295 ; CHECK-P7-NEXT: fmuls 0, 0, 4
296 ; CHECK-P7-NEXT: fmuls 0, 0, 2
297 ; CHECK-P7-NEXT: fmuls 1, 1, 0
359 ; CHECK-P7-NEXT: fmuls 1, 1, 0
386 ; CHECK-P7-NEXT: fmuls 1, 1, 0
[all …]
|
| /external/llvm-project/llvm/test/MC/Sparc/ |
| D | sparc-fp-instructions.s | 80 ! CHECK: fmuls %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x24]
83 fmuls %f0, %f4, %f8
|
| /external/llvm/test/MC/Sparc/ |
| D | sparc-fp-instructions.s | 80 ! CHECK: fmuls %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x24]
83 fmuls %f0, %f4, %f8
|
| /external/capstone/suite/MC/Sparc/ |
| D | sparc-fp-instructions.s.cs | 34 0x91,0xa0,0x09,0x24 = fmuls %f0, %f4, %f8
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | Sparc.td | 30 : SubtargetFeature<"no-fmuls", "HasNoFMULS", "true",
31 "Disable the fmuls instruction.">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | Sparc.td | 30 : SubtargetFeature<"no-fmuls", "HasNoFMULS", "true",
31 "Disable the fmuls instruction.">;
|