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/external/OpenCL-CTS/test_common/harness/
Dfpcontrol.h52 unsigned fpscr; in ForceFTZ()
53 __asm__ volatile("fmrx %0, fpscr" : "=r"(fpscr)); in ForceFTZ()
54 *mode = fpscr; in ForceFTZ()
55 __asm__ volatile("fmxr fpscr, %0" ::"r"(fpscr | (1U << 24))); in ForceFTZ()
58 unsigned fpscr; in ForceFTZ()
59 __asm__ volatile("mrs %0, fpcr" : "=r"(fpscr)); in ForceFTZ()
60 *mode = fpscr; in ForceFTZ()
61 __asm__ volatile("msr fpcr, %0" ::"r"(fpscr | (1U << 24))); in ForceFTZ()
78 unsigned fpscr; in DisableFTZ()
79 __asm__ volatile("fmrx %0, fpscr" : "=r"(fpscr)); in DisableFTZ()
[all …]
Drounding_mode.cpp51 int fpscr = 0; in set_round() local
54 _FPU_GETCW(fpscr); in set_round()
55 _FPU_SETCW(p[r] | (fpscr & ~FPSCR_ROUND_MASK)); in set_round()
62 int fpscr; in get_round() local
65 _FPU_GETCW(fpscr); in get_round()
66 oldRound = (fpscr & FPSCR_ROUND_MASK); in get_round()
212 int fpscr; in FlushToZero()
213 _FPU_GETCW(fpscr); in FlushToZero()
214 _FPU_SETCW(fpscr | FPSCR_FZ); in FlushToZero()
242 int fpscr; in UnFlushToZero()
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dvmrs-vmsr-invalid.txt5 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
9 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
13 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
17 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
21 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
25 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
29 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
33 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
37 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
41 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
[all …]
Darm-vmrs_vmsr.txt19 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
20 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
21 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
22 # CHECK-V7A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
28 # CHECK-V7A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
30 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
31 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
32 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
33 # CHECK-V8A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
39 # CHECK-V8A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
[all …]
Dthumb-vmrs_vmsr.txt27 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
28 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
29 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
30 # CHECK-V7A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
38 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
39 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
40 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
41 # CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
49 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
50 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
[all …]
Dvstrldr_sys.txt17 # CHECK-NOSEC: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
18 # CHECK-NOMVE: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
19 # CHECK-NOVFP: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
20 # CHECK: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
47 # CHECK-NOSEC: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
48 # CHECK-NOMVE: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
49 # CHECK-NOVFP: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
50 # CHECK: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
53 # CHECK-NOSEC: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
54 # CHECK-NOMVE: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dvmrs_vmsr.s22 vmrs APSR_nzcv, fpscr
23 vmrs apsr_nzcv, fpscr
25 vmrs r10, fpscr
31 vmrs sp, fpscr
32 vmrs pc, fpscr
118 vmsr fpscr, APSR_nzcv
119 vmsr fpscr, r0
122 vmsr fpscr, r10
123 vmsr fpscr, sp
124 vmsr fpscr, pc
Dvstrldr_sys.s24 vstr fpscr, [r0]
62 vstrhi fpscr, [r0]
70 vldr fpscr, [r0]
116 vldrhi fpscr, [r0]
442 vldr fpscr, [pc, #4]!
/external/pthreadpool/src/
Dthreadpool-utils.h21 uint32_t fpscr;
34 state.fpscr = (uint32_t) _MoveFromCoprocessor(10, 7, 1, 0, 0); in get_fpu_state()
38 __asm__ __volatile__("VMRS %[fpscr], fpscr" : [fpscr] "=r" (state.fpscr)); in get_fpu_state()
49 _MoveToCoprocessor((int) state.fpscr, 10, 7, 1, 0, 0); in set_fpu_state()
53 __asm__ __volatile__("VMSR fpscr, %[fpscr]" : : [fpscr] "r" (state.fpscr)); in set_fpu_state()
63 int fpscr = _MoveFromCoprocessor(10, 7, 1, 0, 0); in disable_fpu_denormals()
64 fpscr |= 0x1000000; in disable_fpu_denormals()
65 _MoveToCoprocessor(fpscr, 10, 7, 1, 0, 0); in disable_fpu_denormals()
71 uint32_t fpscr; in disable_fpu_denormals()
77 : [fpscr] "=l" (fpscr) in disable_fpu_denormals()
[all …]
/external/llvm-project/compiler-rt/lib/builtins/arm/
Dfp_mode.c31 uint32_t fpscr; in __fe_getround() local
32 __asm__ __volatile__("vmrs %0, fpscr" : "=r" (fpscr)); in __fe_getround()
33 fpscr = fpscr >> ARM_RMODE_SHIFT & ARM_RMODE_MASK; in __fe_getround()
34 switch (fpscr) { in __fe_getround()
52 uint32_t fpscr; in __fe_raise_inexact() local
53 __asm__ __volatile__("vmrs %0, fpscr" : "=r" (fpscr)); in __fe_raise_inexact()
54 __asm__ __volatile__("vmsr fpscr, %0" : : "ri" (fpscr | ARM_INEXACT)); in __fe_raise_inexact()
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvadc-multiple.ll14 %fpscr.in.0 = shl i32 %carry, 29
15 …= call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a.0, <4 x i32> %b.0, i32 %fpscr.in.0)
16 %fpscr.out.0 = extractvalue { <4 x i32>, i32 } %outpair.0, 1
17 %shifted.out.0 = lshr i32 %fpscr.out.0, 29
19 %fpscr.in.1 = shl i32 %carry.out.0, 29
20 …= call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a.1, <4 x i32> %b.1, i32 %fpscr.in.1)
21 %fpscr.out.1 = extractvalue { <4 x i32>, i32 } %outpair.1, 1
22 %shifted.out.1 = lshr i32 %fpscr.out.1, 29
35 %fpscr.in.0 = shl i32 %carry, 29
36 …edicated.v4i32.v4i1(<4 x i32> undef, <4 x i32> %a.0, <4 x i32> %b.0, i32 %fpscr.in.0, <4 x i1> %vp…
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dfpscr-intrinsics.ll9 ; CHECK: vmrs r{{[0-9]+}}, fpscr
25 ; CHECK: vmrs r{{[0-9]+}}, fpscr
26 %0 = tail call i32 @llvm.arm.get.fpscr()
28 ; CHECK: vmsr fpscr, r{{[0-9]+}}
29 tail call void @llvm.arm.set.fpscr(i32 1)
30 ; CHECK: vmrs r{{[0-9]+}}, fpscr
31 %1 = tail call i32 @llvm.arm.get.fpscr()
38 declare i32 @llvm.arm.get.fpscr()
41 declare void @llvm.arm.set.fpscr(i32)
Dinlineasm-X-constraint.ll10 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
15 ; CHECK: vmsr fpscr
22 …call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwi…
29 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
34 ; CHECK: vmsr fpscr
40 call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind
48 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
57 ; unsigned int fpscr;
58 ; asm volatile ("vmsr fpscr,%1" : "=X" ((vector_res_int8x8)) : "r" (fpscr));
63 ; CHECK: vmsr fpscr
[all …]
Dfp16-vminmaxnm-safe.ll11 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
27 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
43 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
59 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
75 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
91 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
107 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
123 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
139 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
155 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
[all …]
Dfcmp-xo.ll10 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
28 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr
61 ; NEON-NEXT: vmrs APSR_nzcv, fpscr
74 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
93 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
Dvsel-fp16.ll111 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
135 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
159 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
183 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
207 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
231 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
255 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
279 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
303 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
327 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
[all …]
/external/FP16/bench/
Dto-alt-array.cc67 unsigned int fpscr; in hardware_vcvt_f16_f32() local
68 __asm__ __volatile__ ("VMRS %[fpscr], fpscr" : [fpscr] "=r" (fpscr)); in hardware_vcvt_f16_f32()
71 : [fpscr] "r" ((fpscr & 0xFEFFFFFFu) | 0x08000000u)); in hardware_vcvt_f16_f32()
81 __asm__ __volatile__ ("VMSR fpscr, %[fpscr]" :: [fpscr] "r" (fpscr)); in hardware_vcvt_f16_f32()
Dfrom-alt-array.cc151 unsigned int fpscr; in hardware_vcvt_f32_f16() local
152 __asm__ __volatile__ ("VMRS %[fpscr], fpscr" : [fpscr] "=r" (fpscr)); in hardware_vcvt_f32_f16()
155 : [fpscr] "r" ((fpscr & 0xFEFFFFFFu) | 0x08000000u)); in hardware_vcvt_f32_f16()
165 __asm__ __volatile__ ("VMSR fpscr, %[fpscr]" :: [fpscr] "r" (fpscr)); in hardware_vcvt_f32_f16()
/external/llvm/test/CodeGen/ARM/
Dinlineasm-X-constraint.ll10 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
15 ; CHECK: vmsr fpscr
22 …call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwi…
29 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
34 ; CHECK: vmsr fpscr
40 call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind
48 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
57 ; unsigned int fpscr;
58 ; asm volatile ("vmsr fpscr,%1" : "=X" ((vector_res_int8x8)) : "r" (fpscr));
63 ; CHECK: vmsr fpscr
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-vcmpfz.ll10 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
16 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
23 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
31 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
62 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
66 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
73 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
82 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
91 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
125 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
[all …]
Dmve-vcmpf.ll10 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
16 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
23 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
31 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
62 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
66 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
73 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
82 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
91 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
125 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
[all …]
Dmve-vcmpfr.ll10 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
16 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
23 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
31 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
65 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
69 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
76 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
85 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
94 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
131 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
[all …]
Dmve-vecreduce-fminmax.ll47 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
50 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
53 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
56 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
136 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
139 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
142 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
150 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
153 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
160 ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
[all …]
/external/XNNPACK/bench/
Dutils.cc78 uint32_t fpscr; in DisableDenormals()
84 : [fpscr] "=l" (fpscr) in DisableDenormals()
92 : [fpscr] "=r" (fpscr)); in DisableDenormals()
/external/rust/crates/gdbstub/src/arch/ppc/reg/
Dcommon.rs32 pub fpscr: u32, field
67 write_regs!(pc, msr, cr, lr, ctr, xer, fpscr); in gdb_serialize()
109 parse_regs!(0x180..0x19c, pc, msr, cr, lr, ctr, xer, fpscr); in gdb_deserialize()
139 fpscr: 8, in ppc_core_round_trip()

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