Searched refs:fs8 (Results 1 – 23 of 23) sorted by relevance
124 fixed_int8_t fs8; in f() local131 …sel = c ? ss8 : fs8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in e… in f()132 …sel = c ? fs8 : ss8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in e… in f()137 …sel = c ? gs8 : fs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result … in f()138 …sel = c ? fs8 : gs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result … in f()141 …ss8 = ss8 + fs8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in expre… in f()144 …fs8 = fs8 + ss8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in expre… in f()145 …fs8 = fs8 + gs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is a… in f()148 …gs8 = gs8 + fs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is a… in f()150 …ss8 += fs8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in expression… in f()[all …]
58 # CHECK-ASM-AND-OBJ: fnmadd.d fs6, fs7, fs8, fs9, dyn96 # CHECK-ASM-AND-OBJ: fcvt.d.s fs7, fs898 fcvt.d.s fs7, fs899 # CHECK-ASM-AND-OBJ: feq.d a1, fs8, fs9101 feq.d a1, fs8, fs9133 # CHECK-ASM-AND-OBJ: fnmadd.d fs6, fs7, fs8, fs9, rup
53 # CHECK-ASM-AND-OBJ: fnmadd.s fs6, fs7, fs8, fs9, dyn96 # CHECK-ASM-AND-OBJ: feq.s a1, fs8, fs998 feq.s a1, fs8, fs9129 # CHECK-ASM-AND-OBJ: fnmadd.s fs6, fs7, fs8, fs9, rup
53 # CHECK-ASM-AND-OBJ: fnmadd.h fs6, fs7, fs8, fs9, dyn96 # CHECK-ASM-AND-OBJ: feq.h a1, fs8, fs998 feq.h a1, fs8, fs9129 # CHECK-ASM-AND-OBJ: fnmadd.h fs6, fs7, fs8, fs9, rup
66 # CHECK-INST: fnmadd.d fs6, fs7, fs8, fs9, dyn67 # CHECK-ALIAS: fnmadd.d fs6, fs7, fs8, fs9{{[[:space:]]}}
70 # CHECK-INST: fnmadd.h fs6, fs7, fs8, fs9, dyn71 # CHECK-ALIAS: fnmadd.h fs6, fs7, fs8, fs9{{[[:space:]]}}
129 # CHECK-INST: fnmadd.s fs6, fs7, fs8, fs9, dyn130 # CHECK-ALIAS: fnmadd.s fs6, fs7, fs8, fs9{{[[:space:]]}}
130 fsqrt.s fa0, fs8
130 fsqrt.d fa0, fs8
56 ; ILP32-NEXT: flw fs8, 124(a1)60 ; ILP32-NEXT: fsw fs8, 124(a1)126 ; LP64-NEXT: flw fs8, 124(a1)130 ; LP64-NEXT: fsw fs8, 124(a1)175 ; ILP32F-NEXT: fsw fs8, 12(sp)209 ; ILP32F-NEXT: flw fs8, 124(a1)213 ; ILP32F-NEXT: fsw fs8, 124(a1)248 ; ILP32F-NEXT: flw fs8, 12(sp)271 ; LP64F-NEXT: fsw fs8, 12(sp)305 ; LP64F-NEXT: flw fs8, 124(a1)[all …]
52 ; ILP32-NEXT: fld fs8, 248(a1)56 ; ILP32-NEXT: fsd fs8, 248(a1)122 ; LP64-NEXT: fld fs8, 248(a1)126 ; LP64-NEXT: fsd fs8, 248(a1)171 ; ILP32D-NEXT: fsd fs8, 24(sp)205 ; ILP32D-NEXT: fld fs8, 248(a1)209 ; ILP32D-NEXT: fsd fs8, 248(a1)244 ; ILP32D-NEXT: fld fs8, 24(sp)267 ; LP64D-NEXT: fsd fs8, 24(sp)301 ; LP64D-NEXT: fld fs8, 248(a1)[all …]
49 ; CHECK-NEXT: flw fs8, 112(a0)56 ; CHECK-NEXT: fsw fs8, 32(sp)
1119 ; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.1124 ; RV32IF-NEXT: fsw fs8, 12(sp)1125 ; RV32IF-NEXT: fmv.s fs8, fa01127 ; RV32IF-NEXT: fcvt.w.s a0, fs81129 ; RV32IF-NEXT: flw fs8, 12(sp)1136 ; RV64IF-NEXT: fsw fs8, 12(sp)1137 ; RV64IF-NEXT: fmv.s fs8, fa01139 ; RV64IF-NEXT: fcvt.w.s a0, fs81141 ; RV64IF-NEXT: flw fs8, 12(sp)1148 ; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.[all …]
1119 ; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.1124 ; RV32IFD-NEXT: fsd fs8, 8(sp)1125 ; RV32IFD-NEXT: fmv.d fs8, fa01127 ; RV32IFD-NEXT: fcvt.w.d a0, fs81129 ; RV32IFD-NEXT: fld fs8, 8(sp)1136 ; RV64IFD-NEXT: fsd fs8, 8(sp)1137 ; RV64IFD-NEXT: fmv.d fs8, fa01139 ; RV64IFD-NEXT: fcvt.w.d a0, fs81141 ; RV64IFD-NEXT: fld fs8, 8(sp)1148 ; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.[all …]
140 ; CHECK-RV32-F-NEXT: fsw fs8, 12(sp)148 ; CHECK-RV32-F-NEXT: flw fs8, 12(sp)243 ; CHECK-RV32-FD-NEXT: fsd fs8, 24(sp)251 ; CHECK-RV32-FD-NEXT: fld fs8, 24(sp)385 ; CHECK-RV64-F-NEXT: fsw fs8, 12(sp)393 ; CHECK-RV64-F-NEXT: flw fs8, 12(sp)488 ; CHECK-RV64-FD-NEXT: fsd fs8, 24(sp)496 ; CHECK-RV64-FD-NEXT: fld fs8, 24(sp)642 ; CHECK-RV32-F-NEXT: fsw fs8, 24(sp)651 ; CHECK-RV32-F-NEXT: flw fs8, 24(sp)[all …]
27 @d3 = external global double ; assigned to register: fs842 ; CHECK-NEXT: fld fs8, %lo(d3)(a0)
460 ; CHECK-RV32IF-NEXT: fsw fs8, 12(sp)477 ; CHECK-RV32IF-NEXT: flw fs8, 12(sp)653 ; CHECK-RV32IF-NEXT: fsw fs8, 24(sp)671 ; CHECK-RV32IF-NEXT: flw fs8, 24(sp)
41 auto &fs8 = typeid(fixed_int8_t); variable
1testfile-riscv64-dis1.o: elf64-elf_riscv 2 3Disassembly of section .text ...
2898 56: fs8 (fs8), float 64 bits
192 def F24_F : RISCVReg32<24,"f24", ["fs8"]>, DwarfRegNum<[56]>;
215 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>;