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Searched refs:getInstr (Results 1 – 25 of 191) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/
DDebugHandlerBase.cpp231 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
234 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
235 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
236 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
241 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
246 Pred.getInstr()->getDebugExpression()); in beginFunction()
253 if (IsDescribedByReg(I->getInstr())) in beginFunction()
255 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
262 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
264 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp146 MachineInstr &MI1 = *SU.getInstr(); in apply()
155 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
183 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
187 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
207 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
210 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
231 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
273 MachineInstr &L0 = *S0.getInstr(); in apply()
286 MachineInstr &L1 = *S1.getInstr(); in apply()
321 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
[all …]
DHexagonMachineScheduler.cpp74 if (QII.mayBeCurLoad(*SUd->getInstr())) in hasDependence()
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
157 switch (SU->getInstr()->getOpcode()) { in reserveResources()
159 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
181 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
308 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
[all …]
DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
109 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
/external/llvm-project/llvm/lib/CodeGen/AsmPrinter/
DDebugHandlerBase.cpp282 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
285 Entries.front().getInstr()->getParent()->sameSection(&MF->front())) { in beginFunction()
286 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
287 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
288 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
293 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
298 Pred.getInstr()->getDebugExpression()); in beginFunction()
305 if (IsDescribedByReg(I->getInstr())) in beginFunction()
307 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
314 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
[all …]
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/X86/
DSnippetGeneratorTest.cpp52 const Instruction &Instr = State.getIC().getInstr(Opcode); in checkAndGetCodeTemplates()
153 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
210 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
361 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
375 const Instruction &getInstr(unsigned Opcode) { in getInstr() function in llvm::exegesis::__anon4a42deb60111::FakeSnippetGenerator
376 return State.getIC().getInstr(Opcode); in getInstr()
380 return {&getInstr(Opcode)}; in getInstructionTemplate()
416 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
431 IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX); in TEST_F()
446 Mov.getValueFor(Mov.getInstr().Variables[0]) = in TEST_F()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCMachineScheduler.cpp31 if (isADDIInstr(*FirstCand.SU->getInstr()) && in biasAddiLoadCandidate()
32 SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
36 if (FirstCand.SU->getInstr()->mayLoad() && in biasAddiLoadCandidate()
37 isADDIInstr(*SecondCand.SU->getInstr())) { in biasAddiLoadCandidate()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp216 MachineInstr &MI1 = *SU.getInstr(); in apply()
225 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
253 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
257 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
277 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
280 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
301 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
343 MachineInstr &L0 = *S0.getInstr(); in apply()
356 MachineInstr &L1 = *S1.getInstr(); in apply()
395 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
[all …]
DHexagonMachineScheduler.cpp74 if (QII.mayBeCurLoad(*SUd->getInstr())) in hasDependence()
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
157 switch (SU->getInstr()->getOpcode()) { in reserveResources()
159 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
181 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
308 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
[all …]
DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
109 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DSnippetGenerator.cpp48 if (Variant.getInstr().hasMemoryOperands()) { in generateConfigurations()
59 for (const auto &Op : Variant.getInstr().Operands) { in generateConfigurations()
121 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
131 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
144 const AliasingConfigurations SelfAliasing(Variant.getInstr(), in generateSelfAliasingCodeTemplates()
145 Variant.getInstr()); in generateSelfAliasingCodeTemplates()
264 for (const Variable &Var : IT.getInstr().Variables) { in randomizeUnsetVariables()
267 if (auto Err = randomizeMCOperand(State, IT.getInstr(), Var, in randomizeUnsetVariables()
DSerialSnippetGenerator.cpp51 const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode); in computeAliasingInstructions()
118 const AliasingConfigurations SelfAliasing(Variant.getInstr(), in appendCodeTemplates()
119 Variant.getInstr()); in appendCodeTemplates()
133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates()
166 getExecutionModes(Variant.getInstr(), ForbiddenRegisters); in generateCodeTemplates()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp161 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
162 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
195 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
220 MachineInstr *MI = SU->getInstr(); in getAluKind()
294 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
323 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
325 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
394 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
443 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp163 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
164 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
198 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
223 MachineInstr *MI = SU->getInstr(); in getAluKind()
296 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
325 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
327 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
396 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
445 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp161 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
162 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
195 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
220 MachineInstr *MI = SU->getInstr(); in getAluKind()
294 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
323 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
325 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
394 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
443 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp30 if (SUnits[su].getInstr()->isCall()) in postprocessDAG()
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) in postprocessDAG()
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
124 DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
249 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
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/external/llvm-project/llvm/lib/CodeGen/
DMacroFusion.cpp94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
161 if (DAG->ExitSU.getInstr()) in apply()
169 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
188 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
DScheduleDAGInstrs.cpp234 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
242 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
264 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
267 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); in addPhysRegDataDeps()
272 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
279 if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle())) in addPhysRegDataDeps()
292 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
317 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
321 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
396 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
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DMachinePipeliner.cpp616 OrderedInsts.push_back(SU->getInstr()); in schedule()
617 Cycles[SU->getInstr()] = Cycle; in schedule()
618 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
744 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
769 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
846 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
902 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
904 if (I.getInstr()->isPHI()) { in updatePhiDependences()
927 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
932 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMacroFusion.cpp94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
161 if (DAG->ExitSU.getInstr()) in apply()
169 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
188 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
DScheduleDAGInstrs.cpp230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
262 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
265 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); in addPhysRegDataDeps()
270 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
277 if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle())) in addPhysRegDataDeps()
290 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
313 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
319 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
394 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
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DMachinePipeliner.cpp536 OrderedInsts.push_back(SU->getInstr()); in schedule()
537 Cycles[SU->getInstr()] = Cycle; in schedule()
538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
665 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
690 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
765 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
821 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
823 if (I.getInstr()->isPHI()) { in updatePhiDependences()
846 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
851 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
[all …]
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()

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