/external/mesa3d/src/amd/compiler/ |
D | aco_opcodes.py | 350 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP2: 351 opcode(name, gfx7, gfx9, gfx10, Format.SOP2) 386 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPK: 387 opcode(name, gfx7, gfx9, gfx10, Format.SOPK) 464 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP1: 465 opcode(name, gfx7, gfx9, gfx10, Format.SOP1) 492 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC: 493 opcode(name, gfx7, gfx9, gfx10, Format.SOPC) 539 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPP: 540 opcode(name, gfx7, gfx9, gfx10, Format.SOPP) [all …]
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/external/llvm-project/clang/test/CodeGenOpenCL/ |
D | amdgpu-features.cl | 45 // GFX1010: "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dpp,+flat-address-space,+gfx10-in… 46 …+dot1-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-insts,+gfx8-insts,… 47 …+dot1-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-insts,+gfx8-insts,… 48 …sts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-3-insts,+gfx10-insts,+gfx8… 49 …sts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-3-insts,+gfx10-insts,+gfx8… 50 …sts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-3-insts,+gfx10-insts,+gfx8… 51 …sts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-3-insts,+gfx10-insts,+gfx8…
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/external/llvm-project/clang/test/SemaOpenCL/ |
D | builtins-amdgcn-error-gfx10.cl | 12 …, c, d, 1, 1); // expected-error {{'__builtin_amdgcn_permlane16' needs target feature gfx10-insts}} 13 …c, d, 1, 1); // expected-error {{'__builtin_amdgcn_permlanex16' needs target feature gfx10-insts}} 14 …mov_dpp8(a, 1); // expected-error {{'__builtin_amdgcn_mov_dpp8' needs target feature gfx10-insts}}
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/external/mesa3d/src/amd/addrlib/ |
D | meson.build | 40 'src/gfx10/gfx10addrlib.cpp', 41 'src/gfx10/gfx10addrlib.h', 42 'src/gfx10/gfx10SwizzlePattern.h', 44 'src/chip/gfx10/gfx10_gb_reg.h', 69 'src/chip/gfx10',
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/external/mesa3d/docs/relnotes/ |
D | 19.2.0.rst | 322 - radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the 325 - radeonsi/gfx10: fix tessellation for the legacy pipeline 326 - radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy 328 - radeonsi/gfx10: create the GS copy shader if using legacy streamout 329 - radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64 330 - radeonsi/gfx10: fix InstanceID for legacy VS+GS 331 - radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0 332 - radeonsi/gfx10: always use the legacy pipeline for streamout 333 - radeonsi/gfx10: finish up Navi14, add PCI ID 334 - radeonsi/gfx10: add AMD_DEBUG=nongg [all …]
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D | 19.3.0.rst | 2321 - radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the 2324 - radeonsi/gfx10: fix tessellation for the legacy pipeline 2325 - radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy 2327 - radeonsi/gfx10: create the GS copy shader if using legacy streamout 2328 - radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64 2329 - radeonsi/gfx10: fix InstanceID for legacy VS+GS 2330 - radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0 2331 - radeonsi/gfx10: always use the legacy pipeline for streamout 2332 - radeonsi/gfx10: finish up Navi14, add PCI ID 2333 - radeonsi/gfx10: add AMD_DEBUG=nongg [all …]
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D | 19.2.1.rst | 122 - radeonsi/gfx10: fix L2 cache rinse programming 126 - radeonsi/gfx10: fix corruption for chips with harvested TCCs
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D | 20.0.3.rst | 158 - radv/gfx10: fix required subgroup size with 160 - radv/gfx10: fix required ballot size with
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D | 19.2.7.rst | 72 - radv/gfx10: fix implementation of exclusive scans
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D | 19.3.3.rst | 149 - ac/gpu_info: always use distributed tessellation on gfx10 202 - aco/gfx10: Fix VcmpxExecWARHazard mitigation.
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D | 20.0.0.rst | 2289 - radeonsi/gfx10: simplify some duplicated NGG GS code 2290 - radeonsi/gfx10: fix the vertex order for triangle strips emitted by a 2311 - radeonsi/gfx10: disable vertex grouping 2312 - radeonsi/gfx10: simplify the tess_turns_off_ngg condition 2321 - radeonsi/gfx10: don't insert NGG streamout atomics if they are never 2327 - radeonsi/gfx10: fix ngg_get_ordered_id 2330 - radeonsi/gfx10: don't declare any LDS for NGG if it's not used 2331 - radeonsi/gfx10: enable NGG passthrough for eligible shaders 2332 - radeonsi/gfx10: improve performance for TES using PrimID but not 2338 gfx10 [all …]
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D | 19.2.5.rst | 102 - radeonsi: disable sdma for gfx10
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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
D | llvm.amdgcn.ds.ordered.add.gfx10.ll | 1 …g < %S/../llvm.amdgcn.ds.ordered.add.gfx10.ll | FileCheck -check-prefixes=GCN %S/../llvm.amdgcn.ds…
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D | inst-select-uadde.gfx10.mir | 4 # These violate the constant bus restriction pre-gfx10
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D | inst-select-usube.gfx10.mir | 4 # These violate the constant bus restriction pre-gfx10
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/external/mesa3d/src/amd/ |
D | Makefile.sources | 26 addrlib/src/gfx10/gfx10addrlib.cpp \ 27 addrlib/src/gfx10/gfx10addrlib.h \ 28 addrlib/src/gfx10/gfx10SwizzlePattern.h \ 29 addrlib/src/chip/gfx10/gfx10_gb_reg.h \
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D | Android.common.mk | 54 $(LOCAL_PATH)/registers/gfx10.json \ 57 $(LOCAL_PATH)/registers/gfx10-rsrc.json \ 83 $(MESA_TOP)/src/amd/registers/gfx10-rsrc.json
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D | Android.addrlib.mk | 43 $(MESA_TOP)/src/amd/addrlib/src/chip/gfx10 \
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/external/mesa3d/src/amd/common/ |
D | meson.build | 28 '../registers/gfx10.json', 33 '../registers/gfx10-rsrc.json', 57 '../../util/format/u_format.csv', '../registers/gfx10-rsrc.json'
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/external/llvm-project/llvm/test/tools/llvm-objdump/ELF/AMDGPU/ |
D | kd-zeroed-raw.s | 6 ;; Not running lit-test over gfx10 (see kd-zeroed-gfx10.s for details).
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/external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
D | branch-relaxation-inst-size-gfx10.ll | 23 ; Estimated as 40-bytes on gfx10 (requiring a long branch), but
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D | waitcnt-overflow.mir | 15 # Overflows lgkmcnt with gfx9 but not with gfx10. 68 # Overflows vmcnt with gfx9 and gfx10.
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/external/llvm-project/clang/include/clang/Basic/ |
D | BuiltinsAMDGPU.def | 206 TARGET_BUILTIN(__builtin_amdgcn_permlane16, "UiUiUiUiUiIbIb", "nc", "gfx10-insts") 207 TARGET_BUILTIN(__builtin_amdgcn_permlanex16, "UiUiUiUiUiIbIb", "nc", "gfx10-insts") 208 TARGET_BUILTIN(__builtin_amdgcn_mov_dpp8, "UiUiIUi", "nc", "gfx10-insts")
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
D | IntrinsicsAMDGPU.td | 416 // gfx10: bits 24-27 indicate the number of active threads/dwords 904 // bit 2 = dlc on gfx10+), 919 // bit 2 = dlc on gfx10+), 934 // bit 2 = dlc on gfx10+), 950 // bit 2 = dlc on gfx10+), 1067 // bit 2 = dlc on gfx10+), 1081 // bit 2 = dlc on gfx10+), 1095 // bit 2 = dlc on gfx10+), 1110 // bit 2 = dlc on gfx10+),
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | AMDGPU.td | 275 def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts", 281 def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts", 399 "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands" 726 "gfx10", 902 // Bugs present on gfx10.1.
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