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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
3
4# These violate the constant bus restriction pre-gfx10
5
6---
7name: uadde_s32_s1_vsv
8legalized: true
9regBankSelected: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0, $vgpr0
14
15    ; GFX10-LABEL: name: uadde_s32_s1_vsv
16    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
17    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
19    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
20    ; GFX10: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
21    ; GFX10: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
22    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
23    ; GFX10: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
24    ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec
25    ; GFX10: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
26    %0:sgpr(s32) = COPY $sgpr0
27    %1:vgpr(s32) = COPY $vgpr0
28    %2:vgpr(s32) = COPY $vgpr2
29    %3:vgpr(s32) = G_CONSTANT i32 0
30    %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
31    %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
32    %7:vgpr(s32) = G_CONSTANT i32 0
33    %8:vgpr(s32) = G_CONSTANT i32 1
34    %9:vgpr(s32) = G_SELECT %6, %7, %8
35    S_ENDPGM 0, implicit %5, implicit %9
36...
37
38---
39name: uadde_s32_s1_vvs
40legalized: true
41regBankSelected: true
42
43body: |
44  bb.0:
45    liveins: $sgpr0, $vgpr0
46
47    ; GFX10-LABEL: name: uadde_s32_s1_vvs
48    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
49    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
50    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
51    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
52    ; GFX10: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
53    ; GFX10: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
54    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
55    ; GFX10: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
56    ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec
57    ; GFX10: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
58    %0:vgpr(s32) = COPY $vgpr0
59    %1:sgpr(s32) = COPY $sgpr0
60    %2:vgpr(s32) = COPY $vgpr2
61    %3:vgpr(s32) = G_CONSTANT i32 0
62    %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
63    %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
64    %7:vgpr(s32) = G_CONSTANT i32 0
65    %8:vgpr(s32) = G_CONSTANT i32 1
66    %9:vgpr(s32) = G_SELECT %6, %7, %8
67    S_ENDPGM 0, implicit %5, implicit %9
68...
69