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/external/mesa3d/src/amd/compiler/
Daco_opcodes.py350 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP2:
351 opcode(name, gfx7, gfx9, gfx10, Format.SOP2)
386 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPK:
387 opcode(name, gfx7, gfx9, gfx10, Format.SOPK)
464 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP1:
465 opcode(name, gfx7, gfx9, gfx10, Format.SOP1)
492 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
493 opcode(name, gfx7, gfx9, gfx10, Format.SOPC)
539 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPP:
540 opcode(name, gfx7, gfx9, gfx10, Format.SOPP)
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/external/mesa3d/src/amd/common/
Dac_surface.c1294 return surf->u.gfx9.dcc.independent_64B_blocks && !surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
1295 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B; in is_dcc_supported_by_L2()
1300 return !surf->u.gfx9.dcc.independent_64B_blocks && surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
1301 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B; in is_dcc_supported_by_L2()
1308 return surf->u.gfx9.dcc.independent_64B_blocks != surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
1309 (!surf->u.gfx9.dcc.independent_64B_blocks || in is_dcc_supported_by_L2()
1310 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) && in is_dcc_supported_by_L2()
1311 (!surf->u.gfx9.dcc.independent_128B_blocks || in is_dcc_supported_by_L2()
1312 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B); in is_dcc_supported_by_L2()
1319 return surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
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/external/llvm-project/clang/test/CodeGenOpenCL/
Damdgpu-features.cl38 // GFX900: "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-in…
39 // GFX902: "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-in…
40 // GFX904: "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-in…
41 …s,+dl-insts,+dot1-insts,+dot2-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+s-memrealtim…
42 …+dot4-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s…
43 // GFX909: "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-in…
44 // GFX90C: "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-in…
45 …ts,+ci-insts,+dl-insts,+dpp,+flat-address-space,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtim…
46 …dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtim…
47 …dot5-insts,+dot6-insts,+dpp,+flat-address-space,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtim…
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/external/mesa3d/docs/relnotes/
D17.3.3.rst58 - Revert "radv/gfx9: fix block compression texture views."
69 - radv/gfx9: fix 3d image to image transfers on compute queues.
70 - radv/gfx9: fix 3d image clears on compute queues
71 - radv/gfx9: fix buffer to image for 3d images on compute queues
72 - radv/gfx9: fix block compression texture views.
73 - radv/gfx9: use a bigger hammer to flush cb/db caches.
74 - radv/gfx9: use correct swizzle parameter to work out border swizzle.
D17.2.1.rst67 - radv: disable 1d/2d linear optimisation on gfx9.
68 - radv/gfx9: set descriptor up for base_mip to level range.
71 - radv/gfx9: allocate events from uncached VA space
75 - radv/gfx9: set mip0-depth correctly for 2d arrays/3d images
77 - radv/gfx9: fix image resource handling.
84 - cherry-ignore: ignore gfx9 tile swizzle fix
128 - radeonsi/gfx9: always flush DB metadata on framebuffer changes
D17.3.2.rst50 - radv/gfx9: add support for 3d images to blit 2d paths
54 - radv/gfx9: add 3d sampler image->buffer copy shader. (v3)
73 - radv/gfx9: fix primitive topology when adjacency is used
D17.1.10.rst52 - cherry-ignore: add "radv: gfx9 fixes"
53 - cherry-ignore: add "radv/gfx9: set mip0-depth correctly for 2d
55 - cherry-ignore: add "radv/gfx9: fix image resource handling."
100 - cherry-ignore: add "ac/surface: handle S8 on gfx9"
D17.2.5.rst91 - radeon/video: add gfx9 offsets when rejoin the video surface
97 - ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
109 - amd/common/gfx9: workaround DCC corruption more conservatively
D17.1.6.rst94 - cherry-ignore: add a couple of radeonsi/gfx9 commits
164 - radeonsi/gfx9: fix crash building monolithic merged ES-GS shader
166 - radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+
D17.2.2.rst58 - ac/surface: handle S8 on gfx9
63 - radv: add gfx9 scissor workaround
104 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
D17.1.9.rst48 - cherry-ignore: add "radeonsi/gfx9: always flush DB metadata on
52 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
D19.0.4.rst166 - radeonsi/gfx9: set that window_rectangles always roll the context
167 - radeonsi/gfx9: rework the gfx9 scissor bug workaround (v2)
/external/mesa3d/src/amd/vulkan/
Dradv_image.c144 return info->bo_metadata->u.gfx9.scanout; in radv_surface_has_scanout()
326 if (md->u.gfx9.swizzle_mode > 0) in radv_patch_surface_from_metadata()
331 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode; in radv_patch_surface_from_metadata()
642 va += plane->surface.u.gfx9.stencil_offset; in si_set_mutable_tex_desc_fields()
644 va += plane->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
682 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode); in si_set_mutable_tex_desc_fields()
684 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode); in si_set_mutable_tex_desc_fields()
697 meta = plane->surface.u.gfx9.dcc; in si_set_mutable_tex_desc_fields()
709 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode); in si_set_mutable_tex_desc_fields()
710 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch); in si_set_mutable_tex_desc_fields()
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/external/mesa3d/src/gallium/drivers/radeonsi/
Dcik_sdma.c64 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_copy_texture()
65 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset; in si_sdma_v4_copy_texture()
66 unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch; in si_sdma_v4_copy_texture()
67 unsigned src_pitch = ssrc->surface.u.gfx9.surf_pitch; in si_sdma_v4_copy_texture()
68 uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.gfx9.surf_slice_size) / bpp; in si_sdma_v4_copy_texture()
69 uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.gfx9.surf_slice_size) / bpp; in si_sdma_v4_copy_texture()
80 assert(sdst->surface.u.gfx9.surf_offset + dst_slice_pitch * bpp * (dstz + src_box->depth) <= in si_sdma_v4_copy_texture()
82 assert(ssrc->surface.u.gfx9.surf_offset + src_slice_pitch * bpp * (srcz + src_box->depth) <= in si_sdma_v4_copy_texture()
107 src_address += ssrc->surface.u.gfx9.offset[src_level]; in si_sdma_v4_copy_texture()
108 dst_address += sdst->surface.u.gfx9.offset[dst_level]; in si_sdma_v4_copy_texture()
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Dsi_texture.c186 *stride = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe; in si_texture_get_offset()
187 *layer_stride = tex->surface.u.gfx9.surf_slice_size; in si_texture_get_offset()
194 return tex->surface.u.gfx9.surf_offset + box->z * tex->surface.u.gfx9.surf_slice_size + in si_texture_get_offset()
195 tex->surface.u.gfx9.offset[level] + in si_texture_get_offset()
196 (box->y / tex->surface.blk_h * tex->surface.u.gfx9.surf_pitch + in si_texture_get_offset()
316 surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X; in si_init_surface()
612 *value = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe; in si_resource_get_param()
621 *value = tex->surface.u.gfx9.surf_offset + layer * tex->surface.u.gfx9.surf_slice_size; in si_resource_get_param()
747 slice_size = tex->surface.u.gfx9.surf_slice_size; in si_texture_get_handle()
846 tex->surface.surf_size, tex->surface.u.gfx9.surf_slice_size, in si_print_texture_info()
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Dsi_clear.c283 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
293 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
297 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
298 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
301 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
302 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
305 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
306 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
Dsi_compute_blit.c483 ((struct si_texture *)src)->surface.u.gfx9.dcc.pipe_aligned); in si_compute_copy_image()
552 info.block[0] = tex->surface.u.gfx9.dcc_block_width; in si_compute_copy_image()
553 info.block[1] = tex->surface.u.gfx9.dcc_block_height; in si_compute_copy_image()
554 info.block[2] = tex->surface.u.gfx9.dcc_block_depth; in si_compute_copy_image()
625 bool use_uint16 = tex->surface.u.gfx9.dcc_retile_use_uint16; in si_retile_dcc()
626 unsigned num_elements = tex->surface.u.gfx9.dcc_retile_num_elements; in si_retile_dcc()
649 img[2].u.buf.size = tex->surface.u.gfx9.display_dcc_size; in si_retile_dcc()
/external/mesa3d/src/amd/addrlib/
Dmeson.build38 'src/gfx9/gfx9addrlib.cpp',
39 'src/gfx9/gfx9addrlib.h',
45 'src/chip/gfx9/gfx9_gb_reg.h',
68 'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
/external/mesa3d/src/amd/
DMakefile.sources24 addrlib/src/gfx9/gfx9addrlib.cpp \
25 addrlib/src/gfx9/gfx9addrlib.h \
30 addrlib/src/chip/gfx9/gfx9_gb_reg.h \
DAndroid.addrlib.mk42 $(MESA_TOP)/src/amd/addrlib/src/chip/gfx9 \
/external/llvm-project/clang/test/SemaOpenCL/
Dbuiltins-amdgcn-error-gfx9.cl8 …cn_fmed3h(a, b, c); // expected-error {{'__builtin_amdgcn_fmed3h' needs target feature gfx9-insts}}
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dstore-hi16.ll19 ; FIXME: ABI for pre-gfx9
39 ; FIXME: ABI for pre-gfx9
120 ; FIXME: ABI for pre-gfx9
403 ; FIXME: ABI for pre-gfx9
423 ; FIXME: ABI for pre-gfx9
523 ; FIXME: ABI for pre-gfx9
564 ; FIXME: ABI for pre-gfx9
583 ; FIXME: ABI for pre-gfx9
638 ; FIXME: ABI for pre-gfx9
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vce_52.c200 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch in create()
201 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch in create()
202 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16) / 8); // encRefYHeightInQw in create()
276 enc->luma->u.gfx9.surf_offset); // inputPictureLumaAddressHi/Lo in encode()
278 enc->chroma->u.gfx9.surf_offset); // inputPictureChromaAddressHi/Lo in encode()
279 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16)); // encInputFrameYPitch in encode()
280 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch in encode()
281 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch in encode()
Dradeon_vce.c226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); in si_vce_frame_offset()
227 vpitch = align(enc->luma->u.gfx9.surf_height, 16); in si_vce_frame_offset()
455 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in si_vce_create_encoder()
456 align(tmp_surf->u.gfx9.surf_height, 32); in si_vce_create_encoder()
Dradeon_vcn_dec_jpeg.c47 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
49 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
50 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; in radeon_jpeg_get_decode_param()

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