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Searched refs:isCall (Results 1 – 25 of 453) sorted by relevance

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/external/llvm/include/llvm/IR/
DCallSite.h78 bool isCall() const { return I.getInt(); } in isCall() function
224 return (*this)->op_end() - (isCall() ? 1 : 3); in data_operands_end()
247 return isCall() && cast<CallInst>(getInstruction())->isMustTailCall(); in isMustTailCall()
252 return isCall() && cast<CallInst>(getInstruction())->isTailCall(); in isTailCall()
257 return isCall() \
263 if (isCall()) \
281 if (isCall()) in isInlineAsm()
527 if (isCall()) in getOperandBundlesAsDefs()
594 if (isCall()) // Skip Callee in getCallee()
/external/llvm/lib/Target/X86/
DX86VZeroUpper.cpp132 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) in hasYmmReg()
146 assert(MI.isCall() && "Can only be called on call instructions."); in callClobbersAnyYmmReg()
188 bool IsControlFlow = MI.isCall() || MI.isReturn(); in processBasicBlock()
217 if (MI.isCall() && !callClobbersAnyYmmReg(MI)) in processBasicBlock()
DX86PadShortFunction.cpp139 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && in runOnMachineFunction()
194 if (MI.isReturn() && !MI.isCall()) { in cyclesUntilReturn()
/external/llvm/include/llvm/MC/
DMCInstrAnalysis.h50 virtual bool isCall(const MCInst &Inst) const { in isCall() function
51 return Info->get(Inst.getOpcode()).isCall(); in isCall()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrAnalysis.h53 virtual bool isCall(const MCInst &Inst) const { in isCall() function
54 return Info->get(Inst.getOpcode()).isCall(); in isCall()
/external/llvm-project/llvm/include/llvm/MC/
DMCInstrAnalysis.h53 virtual bool isCall(const MCInst &Inst) const { in isCall() function
54 return Info->get(Inst.getOpcode()).isCall(); in isCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86VZeroUpper.cpp155 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmAndZmmRegs(MO)) in hasYmmOrZmmReg()
169 assert(MI.isCall() && "Can only be called on call instructions."); in callHasRegMask()
203 bool IsCall = MI.isCall(); in processBasicBlock()
DX86PadShortFunction.cpp150 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && in runOnMachineFunction()
205 if (MI.isReturn() && !MI.isCall()) { in cyclesUntilReturn()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp94 SU->isCall = Old->isCall; in Clone()
373 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
374 NodeSUnit->isCall = true; in BuildSchedUnits()
391 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
392 NodeSUnit->isCall = true; in BuildSchedUnits()
398 if (NodeSUnit->isCall) in BuildSchedUnits()
866 if (MI->isCall() && DAG->getTarget().Options.EnableDebugEntryValues) in EmitSchedule()
914 if (NewInsn && NewInsn->isCall()) in EmitSchedule()
927 if (NewInsn && NewInsn->isCall()) in EmitSchedule()
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiDelaySlotFiller.cpp200 assert((!MI->isCall() && !MI->isReturn()) && in delayHasHazard()
230 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() in insertDefsUses()
250 if (MI->isCall() || MI->isReturn()) in insertDefsUses()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiDelaySlotFiller.cpp200 assert((!MI->isCall() && !MI->isReturn()) && in delayHasHazard()
230 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() in insertDefsUses()
250 if (MI->isCall() || MI->isReturn()) in insertDefsUses()
/external/llvm/lib/Target/Lanai/
DLanaiDelaySlotFiller.cpp202 assert((!MI->isCall() && !MI->isReturn()) && in delayHasHazard()
232 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() in insertDefsUses()
252 if (MI->isCall() || MI->isReturn()) in insertDefsUses()
/external/llvm-project/llvm/lib/Target/X86/
DX86VZeroUpper.cpp160 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmAndZmmRegs(MO)) in hasYmmOrZmmReg()
174 assert(MI.isCall() && "Can only be called on call instructions."); in callHasRegMask()
208 bool IsCall = MI.isCall(); in processBasicBlock()
DX86PadShortFunction.cpp151 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && in runOnMachineFunction()
206 if (MI.isReturn() && !MI.isCall()) { in cyclesUntilReturn()
/external/llvm/lib/Target/Hexagon/
DHexagonVLIWPacketizer.cpp311 return (MI->getDesc().isTerminator() || MI->getDesc().isCall()); in isControlFlow()
991 MJ->isCall() || MJ->isTerminator(); in cannotCoexistAsymm()
1052 if (I->isCall() || J->isCall()) in hasDeadDependence()
1092 if (MI->isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI)) in hasControlDependence()
1107 (J->isBranch() || J->isCall() || J->isBarrier()); in hasControlDependence()
1181 if (PI->isCall()) { in isLegalToPacketizeTogether()
1251 if (I->isCall() || I->isReturn() || HII->isTailCall(I)) { in isLegalToPacketizeTogether()
1309 if (isDirectJump(I) && !J->isBranch() && !J->isCall() && in isLegalToPacketizeTogether()
1415 if (DepType == SDep::Anti && J->isCall()) { in isLegalToPacketizeTogether()
DHexagonInstrInfoV3.td24 let isCall = 1, hasSideEffects = 1, isPredicable = 1,
40 let isCall = 1, hasSideEffects = 1, isPredicated = 1,
69 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
72 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [PC, R31, R6, R7, P0] in
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td161 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
177 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
181 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
186 let isCall = 1, hasSideEffects = 1, cofMax1 = 1, isCodeGenOnly = 1 in
198 let isCall = 1, hasSideEffects = 1,
238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
352 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
DHexagonVLIWPacketizer.cpp346 return MI.getDesc().isTerminator() || MI.getDesc().isCall(); in isControlFlow()
1114 MJ.isCall() || MJ.isTerminator(); in cannotCoexistAsymm()
1205 if (I.isCall() || J.isCall()) in hasDeadDependence()
1245 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI)) in hasControlDependence()
1260 (J.isBranch() || J.isCall() || J.isBarrier()); in hasControlDependence()
1279 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call"); in hasRegMaskDependence()
1369 if (PI->isCall()) { in isLegalToPacketizeTogether()
1433 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) { in isLegalToPacketizeTogether()
1493 if (isDirectJump(I) && !J.isBranch() && !J.isCall() && in isLegalToPacketizeTogether()
1591 if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) { in isLegalToPacketizeTogether()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td161 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
177 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
181 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
186 let isCall = 1, hasSideEffects = 1, cofMax1 = 1, isCodeGenOnly = 1 in
198 let isCall = 1, hasSideEffects = 1,
238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
352 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
DHexagonVLIWPacketizer.cpp338 return MI.getDesc().isTerminator() || MI.getDesc().isCall(); in isControlFlow()
1107 MJ.isCall() || MJ.isTerminator(); in cannotCoexistAsymm()
1198 if (I.isCall() || J.isCall()) in hasDeadDependence()
1238 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI)) in hasControlDependence()
1253 (J.isBranch() || J.isCall() || J.isBarrier()); in hasControlDependence()
1272 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call"); in hasRegMaskDependence()
1362 if (PI->isCall()) { in isLegalToPacketizeTogether()
1426 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) { in isLegalToPacketizeTogether()
1486 if (isDirectJump(I) && !J.isBranch() && !J.isCall() && in isLegalToPacketizeTogether()
1584 if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) { in isLegalToPacketizeTogether()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp95 SU->isCall = Old->isCall; in Clone()
376 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
377 NodeSUnit->isCall = true; in BuildSchedUnits()
394 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
395 NodeSUnit->isCall = true; in BuildSchedUnits()
401 if (NodeSUnit->isCall) in BuildSchedUnits()
923 if (NewInsn && NewInsn->isCall()) in EmitSchedule()
936 if (NewInsn && NewInsn->isCall()) in EmitSchedule()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DCallSite.h87 bool isCall() const { return I.getInt() == 1; } in isCall() function
280 return isCall() && cast<CallInst>(getInstruction())->isMustTailCall(); in isMustTailCall()
285 return isCall() && cast<CallInst>(getInstruction())->isTailCall(); in isTailCall()
290 return isCall() ? cast<CallInst>(II)->METHOD \
296 if (isCall()) \
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrCall.td36 let Uses = [SP32, SP64], isCall = 1 in {
48 } // Uses = [SP32,SP64], isCall = 1
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp94 SU->isCall = Old->isCall; in Clone()
356 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
357 NodeSUnit->isCall = true; in BuildSchedUnits()
374 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
375 NodeSUnit->isCall = true; in BuildSchedUnits()
381 if (NodeSUnit->isCall) in BuildSchedUnits()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp288 if (SU->isCall) { in EmitInstruction()
416 SU.isCall = MI->isCall(); in emitInstruction()

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