| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86RegisterBankInfo.h | 35 static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP);
49 bool isFP) const;
54 const MachineRegisterInfo &MRI, const bool isFP,
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| D | X86RegisterBankInfo.cpp | 66 X86GenRegisterBankInfo::getPartialMappingIdx(const LLT &Ty, bool isFP) { in getPartialMappingIdx() argument
67 if ((Ty.isScalar() && !isFP) || Ty.isPointer()) { in getPartialMappingIdx()
112 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, in getInstrPartialMappingIdxs() argument
121 OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP); in getInstrPartialMappingIdxs()
146 bool isFP) const { in getSameOperandsMapping()
157 auto Mapping = getValueMapping(getPartialMappingIdx(Ty, isFP), 3); in getSameOperandsMapping()
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| D | X86ISelLowering.cpp | 4955 bool isFP, SDValue &LHS, SDValue &RHS, in TranslateX86CC() argument
4957 if (!isFP) { in TranslateX86CC()
22588 bool isFP = Op1.getSimpleValueType().isFloatingPoint(); in LowerVSETCC() local
22591 if (isFP) { in LowerVSETCC()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterBankInfo.h | 35 static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP);
49 bool isFP) const;
54 const MachineRegisterInfo &MRI, const bool isFP,
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| D | X86RegisterBankInfo.cpp | 66 X86GenRegisterBankInfo::getPartialMappingIdx(const LLT &Ty, bool isFP) { in getPartialMappingIdx() argument
67 if ((Ty.isScalar() && !isFP) || Ty.isPointer()) { in getPartialMappingIdx()
112 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, in getInstrPartialMappingIdxs() argument
121 OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP); in getInstrPartialMappingIdxs()
146 bool isFP) const { in getSameOperandsMapping()
157 auto Mapping = getValueMapping(getPartialMappingIdx(Ty, isFP), 3); in getSameOperandsMapping()
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| D | X86ISelLowering.cpp | 4850 bool isFP, SDValue &LHS, SDValue &RHS, in TranslateX86CC() argument
4852 if (!isFP) { in TranslateX86CC()
21360 bool isFP = Op1.getSimpleValueType().isFloatingPoint(); in LowerVSETCC() local
21363 if (isFP) { in LowerVSETCC()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV5.td | 150 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
215 let isPredicateLate = 1, isFP = 1,
238 let isCompare = 1, isFP = 1 in
528 let isFP = 1 in
547 let isFP = 1 in
566 let isFP = 1, hasNewValue = 1 in
586 let isFP = 1, hasNewValue = 1 in
670 let isFP = 1, hasNewValue = 1 in
694 let isFP = 1, hasNewValue = 1 in
726 let isFP = 1, hasNewValue = 1 in
[all …]
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| D | HexagonInstrFormats.td | 171 bits<1> isFP = 0;
172 let TSFlags {48} = isFP; // Floating-point.
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| /external/llvm/utils/TableGen/ |
| D | FastISelEmitter.cpp | 97 bool isFP() const { return Repr == OK_FP; } in isFP() function in __anonf9359ff90311::OperandsSignature::OpKind
106 else if (isFP()) in printManglingSuffix()
291 } else if (Operands[i].isFP()) { in PrintParameters()
318 } else if (Operands[i].isFP()) { in PrintArguments()
333 } else if (Operands[i].isFP()) { in PrintArguments()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | FastISelEmitter.cpp | 107 bool isFP() const { return Repr == OK_FP; } in isFP() function in __anonda4984e70311::OperandsSignature::OpKind
116 else if (isFP()) in printManglingSuffix()
298 } else if (Operands[i].isFP()) { in PrintParameters()
325 } else if (Operands[i].isFP()) { in PrintArguments()
340 } else if (Operands[i].isFP()) { in PrintArguments()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | FLATInstructions.td | 273 bit isFP = isFloatType<data_vt>.ret> {
281 let FPAtomic = isFP;
292 let FPAtomic = isFP;
303 bit isFP = isFloatType<data_vt>.ret> {
313 let FPAtomic = isFP;
325 let FPAtomic = isFP;
336 bit isFP = isFloatType<data_vt>.ret> {
347 let FPAtomic = isFP;
359 let FPAtomic = isFP;
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| D | SIInstrInfo.td | 1465 bit isFP = isFloatType<VT>.ret;
1468 !if(isFP,
1505 bit isFP = isFloatType<VT>.ret;
1508 RegisterOperand ret = !if(isFP, retFlt, retInt);
1514 bit isFP = isFloatType<VT>.ret;
1519 !if(isFP,
1524 !if(isFP,
1561 bit isFP = isFloatType<VT>.ret;
1564 !if(isFP, FP64InputMods, Int64InputMods),
1565 !if(isFP,
[all …]
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| D | BUFInstructions.td | 718 bit isFP = isFloatType<vdataType>.ret> {
719 let FPAtomic = isFP in
723 let FPAtomic = isFP in
727 let FPAtomic = isFP in
730 let FPAtomic = isFP in
734 let FPAtomic = isFP in
742 bit isFP = isFloatType<vdataType>.ret> {
743 let FPAtomic = isFP in
750 let FPAtomic = isFP in
757 let FPAtomic = isFP in
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormats.td | 144 bits<1> isFP = 0;
145 let TSFlags {50} = isFP; // Floating-point.
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| D | HexagonDepInstrInfo.td | 4078 let isFP = 1;
4090 let isFP = 1;
4100 let isFP = 1;
4110 let isFP = 1;
4122 let isFP = 1;
4132 let isFP = 1;
4142 let isFP = 1;
4154 let isFP = 1;
4166 let isFP = 1;
4178 let isFP = 1;
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | FLATInstructions.td | 349 bit isFP = isFloatType<data_vt>.ret> {
357 let FPAtomic = isFP;
369 let FPAtomic = isFP;
381 bit isFP = isFloatType<data_vt>.ret> {
391 let FPAtomic = isFP;
403 let FPAtomic = isFP;
414 bit isFP = isFloatType<data_vt>.ret> {
425 let FPAtomic = isFP;
437 let FPAtomic = isFP;
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| D | SIInstrInfo.td | 1455 bit isFP = isFloatType<VT>.ret;
1458 !if(isFP,
1499 bit isFP = isFloatType<VT>.ret;
1502 RegisterOperand ret = !if(isFP, retFlt, retInt);
1508 bit isFP = isFloatType<VT>.ret;
1513 !if(isFP,
1518 !if(isFP,
1553 bit isFP = isFloatType<VT>.ret;
1556 !if(isFP, FP64InputMods, Int64InputMods),
1557 !if(isFP,
[all …]
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| D | BUFInstructions.td | 726 bit isFP = isFloatType<vdataType>.ret> {
727 let FPAtomic = isFP in
731 let FPAtomic = isFP in
735 let FPAtomic = isFP in
738 let FPAtomic = isFP in
742 let FPAtomic = isFP in
750 bit isFP = isFloatType<vdataType>.ret> {
751 let FPAtomic = isFP in
758 let FPAtomic = isFP in
765 let FPAtomic = isFP in
[all …]
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormats.td | 146 bits<1> isFP = 0;
147 let TSFlags {50} = isFP; // Floating-point.
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| D | HexagonDepInstrInfo.td | 4117 let isFP = 1;
4129 let isFP = 1;
4139 let isFP = 1;
4149 let isFP = 1;
4161 let isFP = 1;
4171 let isFP = 1;
4181 let isFP = 1;
4193 let isFP = 1;
4205 let isFP = 1;
4217 let isFP = 1;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 1582 const bool isFP = Opcode == TargetOpcode::G_FCONSTANT; in select() local
1596 if (isFP) { in select()
1636 if (isFP) { in select()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 2283 const bool isFP = Opcode == TargetOpcode::G_FCONSTANT; in select() local
2297 if (isFP) { in select()
2337 if (isFP) { in select()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3977 bool isFP, SDValue &LHS, SDValue &RHS, in TranslateX86CC() argument
3979 if (!isFP) { in TranslateX86CC()
15253 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint(); in LowerVSETCC() local
15256 if (isFP) { in LowerVSETCC()
15635 bool isFP = Op1.getSimpleValueType().isFloatingPoint(); in LowerSETCC() local
15636 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG); in LowerSETCC()
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