| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 105 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
171 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
|
| D | A15SDOptimizer.cpp | 254 if (MI->isInsertSubreg()) { in optimizeSDPattern()
337 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()
405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
168 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
|
| D | A15SDOptimizer.cpp | 246 if (MI->isInsertSubreg()) { in optimizeSDPattern()
329 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()
397 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
168 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
|
| D | A15SDOptimizer.cpp | 246 if (MI->isInsertSubreg()) { in optimizeSDPattern()
329 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()
397 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
|
| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 67 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
|
| D | PeepholeOptimizer.cpp | 198 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()
968 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()
1765 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()
1904 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
|
| D | TargetInstrInfo.cpp | 1174 assert((MI.isInsertSubreg() || in getInsertSubregInputs()
1177 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 65 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
|
| D | PeepholeOptimizer.cpp | 244 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()
912 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()
1924 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()
2067 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
|
| D | TargetInstrInfo.cpp | 1341 assert((MI.isInsertSubreg() || in getInsertSubregInputs()
1344 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 65 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
|
| D | PeepholeOptimizer.cpp | 241 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()
907 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()
1924 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()
2067 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
|
| D | TargetInstrInfo.cpp | 1268 assert((MI.isInsertSubreg() || in getInsertSubregInputs()
1271 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | InstrDocsEmitter.cpp | 137 FLAG(isInsertSubreg) in EmitInstrDocs()
|
| D | CodeGenInstruction.h | 275 bool isInsertSubreg : 1; variable
|
| D | InstrInfoEmitter.cpp | 782 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; in emitRecord()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 257 bool isInsertSubreg : 1; variable
|
| D | InstrInfoEmitter.cpp | 508 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; in emitRecord()
|
| D | CodeGenInstruction.cpp | 325 isInsertSubreg = R->getValueAsBit("isInsertSubreg"); in CodeGenInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 467 if (isInsertSubreg() && OpIdx == 3)
1099 bool isInsertSubreg() const {
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 553 if (isInsertSubreg() && OpIdx == 3)
1208 bool isInsertSubreg() const {
|
| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 271 return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence(); in shouldSink()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 805 bool isInsertSubreg() const {
|