| /external/mesa3d/src/panfrost/shared/ |
| D | pan_tiling.c | 190 bool is_store) \
202 if (is_store) \
217 #define TILED_UNALIGNED_TYPE(pixel_t, is_store, tile_shift) { \ argument
231 pixel_t *outp = (pixel_t *) (is_store ? dest : source); \
232 pixel_t *inp = (pixel_t *) (is_store ? source : dest); \
289 bool is_store) in panfrost_access_tiled_image() argument
296 dst_stride, src_stride, desc, is_store); in panfrost_access_tiled_image()
316 dst_stride, src_stride, desc, is_store); in panfrost_access_tiled_image()
331 dst_stride, src_stride, desc, is_store); in panfrost_access_tiled_image()
342 dst_stride, src_stride, desc, is_store); in panfrost_access_tiled_image()
[all …]
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info_opcodes.h | 104 OPCODE(1, 3, OTHR, ATOMFADD, .is_store = 1)
164 OPCODE(1, 2, OTHR, STORE, .is_store = 1)
170 OPCODE(1, 3, OTHR, ATOMUADD, .is_store = 1)
171 OPCODE(1, 3, OTHR, ATOMXCHG, .is_store = 1)
172 OPCODE(1, 4, OTHR, ATOMCAS, .is_store = 1)
173 OPCODE(1, 3, OTHR, ATOMAND, .is_store = 1)
174 OPCODE(1, 3, OTHR, ATOMOR, .is_store = 1)
175 OPCODE(1, 3, OTHR, ATOMXOR, .is_store = 1)
176 OPCODE(1, 3, OTHR, ATOMUMIN, .is_store = 1)
177 OPCODE(1, 3, OTHR, ATOMUMAX, .is_store = 1)
[all …]
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| D | tgsi_info.h | 77 unsigned is_store:1; member
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| D | tgsi_scan.c | 305 if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) { in scan_src_operand()
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| /external/mesa3d/src/compiler/nir/ |
| D | nir_lower_ssbo.c | 106 bool is_store = op == nir_intrinsic_store_global; in lower_ssbo_instr() local
107 bool is_atomic = !is_store && op != nir_intrinsic_load_global; in lower_ssbo_instr()
114 nir_src index = intr->src[is_store ? 1 : 0]; in lower_ssbo_instr()
129 global->src[is_store ? 1 : 0] = nir_src_for_ssa(address); in lower_ssbo_instr()
136 if (is_store) { in lower_ssbo_instr()
152 return is_store ? NULL : &global->dest.ssa; in lower_ssbo_instr()
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| D | nir_opt_load_store_vectorize.c | 183 bool is_store; member
263 unsigned size = entry->is_store ? in get_bit_size()
569 entry->is_store = entry->info->value_src >= 0; in create_entry()
657 if (low->is_store) { in new_bitsize_acceptable()
964 if (first->is_store) { in check_for_aliasing()
981 if (prev->is_store && may_alias(second, prev)) in check_for_aliasing()
1079 if (first->is_store) in try_vectorize()
1137 low = low->is_store ? second : first; in vectorize_entries()
1279 if (entry->is_store) { in process_block()
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| /external/llvm-project/compiler-rt/lib/hwasan/ |
| D | hwasan_linux.cpp | 323 bool is_store; member
343 const bool is_store = code & 0x10; in GetAccessInfo() local
362 const bool is_store = code & 0x10; in GetAccessInfo()
375 return AccessInfo{addr, size, is_store, !is_store, recover}; in GetAccessInfo()
396 ReportTagMismatch(stack, ai.addr, ai.size, ai.is_store, fatal, in HandleTagMismatch()
402 if (!ai.is_store && !ai.is_load) in HwasanOnSIGTRAP()
440 ai.is_store = access_info & 0x10; in __hwasan_tag_mismatch4()
441 ai.is_load = !ai.is_store; in __hwasan_tag_mismatch4()
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| D | hwasan_report.h | 25 bool is_store, bool fatal, uptr *registers_frame);
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| D | hwasan_report.cpp | 590 bool is_store, bool fatal, uptr *registers_frame) { in ReportTagMismatch() argument
616 is_store ? "WRITE" : "READ", access_size, untagged_addr, ptr_tag, in ReportTagMismatch()
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| /external/mesa3d/src/broadcom/compiler/ |
| D | v3d_nir_lower_scratch.c | 40 bool is_store = instr->intrinsic == nir_intrinsic_store_scratch; in v3d_nir_scratch_offset() local
41 nir_ssa_def *offset = nir_ssa_for_src(b, instr->src[is_store ? 1 : 0], 1); in v3d_nir_scratch_offset()
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| D | nir_to_vir.c | 225 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo || in ntq_emit_tmu_general() local
249 } else if (is_store) { in ntq_emit_tmu_general()
292 nir_src_as_uint(instr->src[is_store ? in ntq_emit_tmu_general()
297 unsigned writemask = is_store ? nir_intrinsic_write_mask(instr) : 0; in ntq_emit_tmu_general()
304 if (is_store) { in ntq_emit_tmu_general()
430 } while (is_store && writemask != 0); in ntq_emit_tmu_general()
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| /external/mesa3d/src/panfrost/util/ |
| D | pan_lower_framebuffer.c | 141 pan_format_class(const struct util_format_description *desc, unsigned quirks, bool is_store) in pan_format_class() argument
143 if (is_store) in pan_format_class()
742 bool is_store = intr->intrinsic == nir_intrinsic_store_deref; in pan_lower_framebuffer() local
744 if (!(is_load || (is_store && is_blend))) in pan_lower_framebuffer()
769 pan_format_class(desc, quirks, is_store); in pan_lower_framebuffer()
784 if (is_store) { in pan_lower_framebuffer()
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| /external/mesa3d/src/panfrost/midgard/ |
| D | compiler.h | 567 bool is_store, in v_load_store_scratch() argument
580 .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4, in v_load_store_scratch()
593 if (is_store) { in v_load_store_scratch()
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| /external/mesa3d/src/gallium/auxiliary/nir/ |
| D | nir_to_tgsi.c | 1070 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo || in ntt_emit_mem() local
1086 instr->src[is_store ? 1 : 0]); in ntt_emit_mem()
1097 if (is_store) { in ntt_emit_mem()
1178 if (is_store) { in ntt_emit_mem()
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3.h | 782 is_store(struct ir3_instruction *instr) in is_store() function
903 if ((instr->regs_count == 0) || is_store(instr) || is_flow(instr)) in dest_regs()
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| D | ir3.c | 710 if (is_store(instr)) { in emit_cat6()
1422 if (is_store(instr) && (n == 1)) in ir3_valid_flags()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_nir.cpp | 3999 const bool is_store = in get_nir_ssbo_intrinsic_index() local
4002 const unsigned src = is_store ? 1 : 0; in get_nir_ssbo_intrinsic_index()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 5507 if (inst->info->is_store) in eliminate_dead_code()
|