Searched refs:ldc2l (Results 1 – 25 of 32) sorted by relevance
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4 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ldc2l5 define void @ldc2l(i8* %i) nounwind {7 call void @llvm.arm.ldc2l(i32 1, i32 2, i8* %i) nounwind11 declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
28 ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]29 tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind51 declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
27 ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]28 tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind50 declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
22 ldc2l p1, c2, [r7, #4] label24 ldc2l p0, c1, [r8] label26 ldc2l p1, c0, [r9, #-224] label28 ldc2l p0, c1, [r10, #-120]! label
1080 ldc2l p6, c2, [r7, #4]1081 ldc2l p7, c1, [r8]1082 ldc2l p8, c0, [r9, #-224]1083 ldc2l p9, c1, [r10, #-120]!1084 ldc2l p0, c2, [r11], #161085 ldc2l p1, c3, [r12], #-721121 @ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0x01,0x26,0xd7,0xfd]1122 @ CHECK: ldc2l p7, c1, [r8] @ encoding: [0x00,0x17,0xd8,0xfd]1123 @ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x38,0x08,0x59,0xfd]1124 @ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x1e,0x19,0x7a,0xfd][all …]
874 ldc2l p6, c2, [r7, #4]875 ldc2l p7, c1, [r8]876 ldc2l p8, c0, [r9, #-224]877 ldc2l p9, c1, [r10, #-120]!878 ldc2l p0, c2, [r11], #16879 ldc2l p1, c3, [r12], #-72902 @ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0xd7,0xfd,0x01,0x26]903 @ CHECK: ldc2l p7, c1, [r8] @ encoding: [0xd8,0xfd,0x00,0x17]904 @ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x59,0xfd,0x38,0x08]905 @ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x7a,0xfd,0x1e,0x19][all …]
369 ldc2l p6, c2, [r7, #4]
26 ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]27 tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind65 declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
110 void ldc2l(const void *i) { in ldc2l() function
50 # NOBF16-NEXT: ldc2l p8, c0, [r0], #-32078 # NOBF16-NEXT: ldc2l p8, c0, [r0], #-64
125 void ldc2l(const void *i) { in ldc2l() function
225 0xd7,0xfd,0x01,0x26 = ldc2l p6, c2, [r7, #4]226 0xd8,0xfd,0x00,0x17 = ldc2l p7, c1, [r8]227 0x59,0xfd,0x38,0x08 = ldc2l p8, c0, [r9, #-224]228 0x7a,0xfd,0x1e,0x19 = ldc2l p9, c1, [r10, #-120]!229 0xfb,0xfc,0x04,0x20 = ldc2l p0, c2, [r11], #16230 0x7c,0xfc,0x12,0x31 = ldc2l p1, c3, [r12], #-72
285 0x01,0x26,0xd7,0xfd = ldc2l p6, c2, [r7, #4]286 0x00,0x17,0xd8,0xfd = ldc2l p7, c1, [r8]287 0x38,0x08,0x59,0xfd = ldc2l p8, c0, [r9, #-224]288 0x1e,0x19,0x7a,0xfd = ldc2l p9, c1, [r10, #-120]!289 0x04,0x20,0xfb,0xfc = ldc2l p0, c2, [r11], #16290 0x12,0x31,0x7c,0xfc = ldc2l p1, c3, [r12], #-72
1078 ldc2l p6, c2, [r7, #4]1079 ldc2l p7, c1, [r8]1080 ldc2l p8, c0, [r9, #-224]1081 ldc2l p9, c1, [r10, #-120]!1082 ldc2l p0, c2, [r11], #161083 ldc2l p1, c3, [r12], #-721119 @ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0x01,0x26,0xd7,0xfd]1120 @ CHECK: ldc2l p7, c1, [r8] @ encoding: [0x00,0x17,0xd8,0xfd]1121 @ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x38,0x08,0x59,0xfd]1122 @ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x1e,0x19,0x7a,0xfd][all …]
746 ldc2l p6, c2, [r7, #4]747 ldc2l p7, c1, [r8]748 ldc2l p8, c0, [r9, #-224]749 ldc2l p9, c1, [r10, #-120]!750 ldc2l p0, c2, [r11], #16751 ldc2l p1, c3, [r12], #-72774 @ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0xd7,0xfd,0x01,0x26]775 @ CHECK: ldc2l p7, c1, [r8] @ encoding: [0xd8,0xfd,0x00,0x17]776 @ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x59,0xfd,0x38,0x08]777 @ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x7a,0xfd,0x1e,0x19][all …]
277 ldc2l p6, c2, [r7, #4]
253 { /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr */256 { /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $option */259 { /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $offset */262 { /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr! */5509 { /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr */5512 { /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $option */5515 { /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $offset */5518 { /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr! */
9888 "dc\004ldc2\005ldc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004"10578 …{ 511 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsA…10579 …{ 511 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCod…10580 …{ 511 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_…10581 …{ 511 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocO…10582 …{ 511 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxIm…10583 …{ 511 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_…10584 …{ 511 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__Copro…10585 …{ 511 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdx…15460 { 511 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },[all …]
4012 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr…
5016 defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requir…
4245 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$ad…
4314 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$ad…
5517 defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requ…