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Searched refs:ldcl (Results 1 – 25 of 29) sorted by relevance

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/external/llvm-project/libunwind/src/
DUnwindRegistersRestore.S722 ldcl p1, cr0, [r0], #8 @ wldrd wR0, [r0], #8
723 ldcl p1, cr1, [r0], #8 @ wldrd wR1, [r0], #8
724 ldcl p1, cr2, [r0], #8 @ wldrd wR2, [r0], #8
725 ldcl p1, cr3, [r0], #8 @ wldrd wR3, [r0], #8
726 ldcl p1, cr4, [r0], #8 @ wldrd wR4, [r0], #8
727 ldcl p1, cr5, [r0], #8 @ wldrd wR5, [r0], #8
728 ldcl p1, cr6, [r0], #8 @ wldrd wR6, [r0], #8
729 ldcl p1, cr7, [r0], #8 @ wldrd wR7, [r0], #8
730 ldcl p1, cr8, [r0], #8 @ wldrd wR8, [r0], #8
731 ldcl p1, cr9, [r0], #8 @ wldrd wR9, [r0], #8
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll23 ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
24 tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
46 declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
/external/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll24 ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
25 tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
47 declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dintrinsics-coprocessor.ll22 ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
23 tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
61 declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
/external/clang/test/CodeGen/
Dbuiltins-arm.c96 void ldcl(const void *i) { in ldcl() function
/external/llvm-project/clang/test/CodeGen/
Dbuiltins-arm.c111 void ldcl(const void *i) { in ldcl() function
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs237 0xd6,0xed,0x01,0xa3 = ldcl p3, c10, [r6, #4]
238 0xd7,0xed,0x00,0xb2 = ldcl p2, c11, [r7]
239 0x58,0xed,0x38,0xc1 = ldcl p1, c12, [r8, #-224]
240 0x79,0xed,0x1e,0xd0 = ldcl p0, c13, [r9, #-120]!
241 0xfa,0xec,0x04,0xe6 = ldcl p6, c14, [r10], #16
242 0x7b,0xec,0x12,0xf7 = ldcl p7, c15, [r11], #-72
Dbasic-arm-instructions.s.cs297 0x01,0xa3,0xd6,0xed = ldcl p3, c10, [r6, #4]
298 0x00,0xb2,0xd7,0xed = ldcl p2, c11, [r7]
299 0x38,0xc1,0x58,0xed = ldcl p1, c12, [r8, #-224]
300 0x1e,0xd0,0x79,0xed = ldcl p0, c13, [r9, #-120]!
301 0x04,0xe6,0xfa,0xec = ldcl p6, c14, [r10], #16
302 0x12,0xf7,0x7b,0xec = ldcl p7, c15, [r11], #-72
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1093 ldcl p3, c10, [r6, #4]
1094 ldcl p2, c11, [r7]
1095 ldcl p1, c12, [r8, #-224]
1096 ldcl p0, c13, [r9, #-120]!
1097 ldcl p6, c14, [r10], #16
1098 ldcl p7, c15, [r11], #-72
1134 @ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xd6,0xed]
1135 @ CHECK: ldcl p2, c11, [r7] @ encoding: [0x00,0xb2,0xd7,0xed]
1136 @ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x58,0xed]
1137 @ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x79,0xed]
[all …]
Dbasic-thumb2-instructions.s887 ldcl p3, c10, [r6, #4]
888 ldcl p2, c11, [r7]
889 ldcl p1, c12, [r8, #-224]
890 ldcl p0, c13, [r9, #-120]!
891 ldcl p6, c14, [r10], #16
892 ldcl p7, c15, [r11], #-72
915 @ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0xd6,0xed,0x01,0xa3]
916 @ CHECK: ldcl p2, c11, [r7] @ encoding: [0xd7,0xed,0x00,0xb2]
917 @ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x58,0xed,0x38,0xc1]
918 @ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x79,0xed,0x1e,0xd0]
[all …]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1091 ldcl p3, c10, [r6, #4]
1092 ldcl p2, c11, [r7]
1093 ldcl p1, c12, [r8, #-224]
1094 ldcl p0, c13, [r9, #-120]!
1095 ldcl p6, c14, [r10], #16
1096 ldcl p7, c15, [r11], #-72
1132 @ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xd6,0xed]
1133 @ CHECK: ldcl p2, c11, [r7] @ encoding: [0x00,0xb2,0xd7,0xed]
1134 @ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x58,0xed]
1135 @ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x79,0xed]
[all …]
Dbasic-thumb2-instructions.s759 ldcl p3, c10, [r6, #4]
760 ldcl p2, c11, [r7]
761 ldcl p1, c12, [r8, #-224]
762 ldcl p0, c13, [r9, #-120]!
763 ldcl p6, c14, [r10], #16
764 ldcl p7, c15, [r11], #-72
787 @ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0xd6,0xed,0x01,0xa3]
788 @ CHECK: ldcl p2, c11, [r7] @ encoding: [0xd7,0xed,0x00,0xb2]
789 @ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x58,0xed,0x38,0xc1]
790 @ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x79,0xed,0x1e,0xd0]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Darm-tests.txt57 # CHECK: ldcl p1, c9, [r3, #0]!
/external/llvm/test/MC/Disassembler/ARM/
Darm-tests.txt57 # CHECK: ldcl p1, c9, [r3, #0]!
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc277 { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */
280 { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */
283 { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */
286 { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */
5533 { /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */
5536 { /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */
5539 { /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */
5542 { /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc277 { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */
280 { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */
283 { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */
286 { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */
5533 { /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */
5536 { /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */
5539 { /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */
5542 { /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9888 "dc\004ldc2\005ldc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004"
10586 …{ 517 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0…
10587 …{ 517 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2…
10588 …{ 517 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, A…
10589 …{ 517 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,…
10590 …{ 517 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOpt…
10591 …{ 517 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocO…
10592 …{ 517 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8…
10593 …{ 517 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxIm…
15478 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4010 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]…
DARMInstrInfo.td5014 defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td4243 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr…
DARMInstrInfo.td5365 defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td4312 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr…
DARMInstrInfo.td5515 defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen546 arm_ldcl, // llvm.arm.ldcl
6604 "llvm.arm.ldcl",
14544 3, // llvm.arm.ldcl
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen546 arm_ldcl, // llvm.arm.ldcl
6604 "llvm.arm.ldcl",
14544 3, // llvm.arm.ldcl

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