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Searched refs:loadaddr (Results 1 – 23 of 23) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/ARM/
Dvcvt-cost.ll8 define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
12 %v0 = load %T0_5, %T0_5* %loadaddr
24 define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
28 %v0 = load %TA0_5, %TA0_5* %loadaddr
39 define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
43 %v0 = load %T0_51, %T0_51* %loadaddr
54 define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
59 %v0 = load %TT0_5, %TT0_5* %loadaddr
71 define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
76 %v0 = load %TTA0_5, %TTA0_5* %loadaddr
[all …]
Dbig-endian-neon-extend.ll3 define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
12 %1 = load <2 x i8>, <2 x i8>* %loadaddr
18 define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
26 %1 = load <2 x i16>, <2 x i16>* %loadaddr
33 define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
42 %1 = load <2 x i8>, <2 x i8>* %loadaddr
48 define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
56 %1 = load <2 x i16>, <2 x i16>* %loadaddr
62 define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
73 %1 = load <2 x i8>, <2 x i8>* %loadaddr
[all …]
Dbig-endian-neon-trunc-store.ll3 define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* %storeaddr ) {
9 %1 = load <2 x i64>, <2 x i64>* %loadaddr
15 define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %storeaddr ) {
21 %1 = load <4 x i32>, <4 x i32>* %loadaddr
Dneon_fpconv.ll20 define void @vsitofp_double(<2 x i32>* %loadaddr,
22 %v0 = load <2 x i32>, <2 x i32>* %loadaddr
32 define void @vuitofp_double(<2 x i32>* %loadaddr,
34 %v0 = load <2 x i32>, <2 x i32>* %loadaddr
Dvselect_imax.ll16 define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
18 %v0 = load %T0_10, %T0_10* %loadaddr
32 define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
34 %v0 = load %T0_14, %T0_14* %loadaddr
48 define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
52 %v0 = load %T0_15, %T0_15* %loadaddr
66 define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
126 %v0 = load %T0_18, %T0_18* %loadaddr
137 define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
255 %v0 = load %T0_19, %T0_19* %loadaddr
[all …]
Dvector-DAGCombine.ll148 define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
149 %v0 = load <8 x i16>, <8 x i16>* %loadaddr
161 define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
162 %v0 = load <16 x i8>, <16 x i8>* %loadaddr
/external/llvm/test/CodeGen/ARM/
Dvcvt-cost.ll8 define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
12 %v0 = load %T0_5, %T0_5* %loadaddr
24 define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
28 %v0 = load %TA0_5, %TA0_5* %loadaddr
39 define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
43 %v0 = load %T0_51, %T0_51* %loadaddr
54 define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
59 %v0 = load %TT0_5, %TT0_5* %loadaddr
71 define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
76 %v0 = load %TTA0_5, %TTA0_5* %loadaddr
[all …]
Dbig-endian-neon-extend.ll3 define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
12 %1 = load <2 x i8>, <2 x i8>* %loadaddr
18 define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
26 %1 = load <2 x i16>, <2 x i16>* %loadaddr
33 define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
42 %1 = load <2 x i8>, <2 x i8>* %loadaddr
48 define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
56 %1 = load <2 x i16>, <2 x i16>* %loadaddr
62 define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
73 %1 = load <2 x i8>, <2 x i8>* %loadaddr
[all …]
Dvselect_imax.ll16 define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
18 %v0 = load %T0_10, %T0_10* %loadaddr
32 define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
34 %v0 = load %T0_14, %T0_14* %loadaddr
48 define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
52 %v0 = load %T0_15, %T0_15* %loadaddr
67 define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
71 %v0 = load %T0_18, %T0_18* %loadaddr
83 define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
89 %v0 = load %T0_19, %T0_19* %loadaddr
[all …]
Dbig-endian-neon-trunc-store.ll3 define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* %storeaddr ) {
9 %1 = load <2 x i64>, <2 x i64>* %loadaddr
15 define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %storeaddr ) {
21 %1 = load <4 x i32>, <4 x i32>* %loadaddr
Dneon_fpconv.ll20 define void @vsitofp_double(<2 x i32>* %loadaddr,
22 %v0 = load <2 x i32>, <2 x i32>* %loadaddr
32 define void @vuitofp_double(<2 x i32>* %loadaddr,
34 %v0 = load <2 x i32>, <2 x i32>* %loadaddr
Dvector-DAGCombine.ll148 define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
149 %v0 = load <8 x i16>, <8 x i16>* %loadaddr
161 define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
162 %v0 = load <16 x i8>, <16 x i8>* %loadaddr
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dadd-cast-vect.ll17 define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
19 %v0 = load %T432, %T432* %loadaddr
31 define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
33 %v0 = load %T416, %T416* %loadaddr
48 define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
50 %v0 = load %T416, %T416* %loadaddr
65 define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
67 %v0 = load %T232, %T232* %loadaddr
82 define void @upu3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
84 %v0 = load %T232, %T232* %loadaddr
[all …]
Dshl-cast-vect.ll18 define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
20 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, <4 x i32>* %loadaddr, align 8
26 %v0 = load %T432, %T432* %loadaddr
37 define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
39 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8
47 %v0 = load %T416, %T416* %loadaddr
60 define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
62 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8
70 %v0 = load %T416, %T416* %loadaddr
83 define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
[all …]
Dmul-cast-vect.ll18 define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
20 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, <4 x i32>* %loadaddr, align 8
26 %v0 = load %T432, %T432* %loadaddr
37 define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
39 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8
47 %v0 = load %T416, %T416* %loadaddr
60 define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
62 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8
70 %v0 = load %T416, %T416* %loadaddr
83 define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
[all …]
Dsub-cast-vect.ll18 define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
20 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, <4 x i32>* %loadaddr, align 8
26 %v0 = load %T432, %T432* %loadaddr
37 define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
39 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8
47 %v0 = load %T416, %T416* %loadaddr
60 define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
62 …: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8
70 %v0 = load %T416, %T416* %loadaddr
83 define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
[all …]
/external/llvm/test/Transforms/LoopVectorize/ARM/
Dmul-cast-vect.ll17 define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
19 %v0 = load %T432, %T432* %loadaddr
31 define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
33 %v0 = load %T416, %T416* %loadaddr
48 define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
50 %v0 = load %T416, %T416* %loadaddr
65 define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
67 %v0 = load %T232, %T232* %loadaddr
82 define void @upu3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
84 %v0 = load %T232, %T232* %loadaddr
[all …]
/external/arm-trusted-firmware/tools/stm32image/
Dstm32image.c108 uint32_t loadaddr, uint32_t ep, uint32_t ver) in stm32image_set_header() argument
114 stm32hdr->load_address = __cpu_to_le32(loadaddr); in stm32image_set_header()
123 uint32_t loadaddr, uint32_t entry, in stm32image_create_header_file() argument
184 stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, entry, version); in stm32image_create_header_file()
195 int opt, loadaddr = -1, entry = -1, err = 0, version = 0; in main() local
207 loadaddr = strtol(optarg, NULL, 16); in main()
233 if (loadaddr == -1) { in main()
243 err = stm32image_create_header_file(src, dest, loadaddr, in main()
/external/bcc/src/lua/bpf/spec/
Delf_spec.lua11 local base = sh:loadaddr()
22 assert.falsy(elf.open('/tmp'):loadaddr())
/external/bcc/src/lua/bpf/
Delf.lua192 loadaddr = function(t) function
Dbpf.lua1614 sym = sym.st_value - elf:loadaddr()
/external/tensorflow/tensorflow/lite/micro/tools/make/targets/arc/
DREADME.md236 setenv loadaddr 0x10800000
239 setenv bootcmd fatload mmc 0 \$\{loadaddr\} \$\{bootfile\} \&\& bootelf
/external/tensorflow/tensorflow/lite/micro/examples/person_detection/
DREADME.md104 loadaddr 0x10800000 setenv bootfile app.elf setenv bootdelay 1 setenv
105 bootcmd fatload mmc 0 \$\{loadaddr\} \$\{bootfile\} \&\& bootelf