1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py 2; RUN: opt < %s -cost-model -analyze -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s 3; To see the assembly output: llc -mcpu=cortex-a9 < %s | FileCheck --check-prefix=ASM %s 4; ASM lines below are only for reference, tests on that direction should go to tests/CodeGen/ARM 5 6; ModuleID = 'arm.ll' 7target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" 8target triple = "armv7--linux-gnueabihf" 9 10%T216 = type <2 x i16> 11%T232 = type <2 x i32> 12%T264 = type <2 x i64> 13 14%T416 = type <4 x i16> 15%T432 = type <4 x i32> 16%T464 = type <4 x i64> 17 18define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) { 19; COST-LABEL: 'direct' 20; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, <4 x i32>* %loadaddr, align 8 21; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, <4 x i32>* %loadaddr2, align 8 22; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %v0, %v1 23; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, <4 x i32>* %storeaddr, align 8 24; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void 25; 26 %v0 = load %T432, %T432* %loadaddr 27; ASM: vld1.64 28 %v1 = load %T432, %T432* %loadaddr2 29; ASM: vld1.64 30 %r3 = mul %T432 %v0, %v1 31; ASM: vmul.i32 32 store %T432 %r3, %T432* %storeaddr 33; ASM: vst1.64 34 ret void 35} 36 37define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) { 38; COST-LABEL: 'ups1632' 39; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8 40; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, <4 x i16>* %loadaddr2, align 8 41; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = sext <4 x i16> %v0 to <4 x i32> 42; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext <4 x i16> %v1 to <4 x i32> 43; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %r1, %r2 44; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, <4 x i32>* %storeaddr, align 8 45; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void 46; 47 %v0 = load %T416, %T416* %loadaddr 48; ASM: vldr 49 %v1 = load %T416, %T416* %loadaddr2 50; ASM: vldr 51 %r1 = sext %T416 %v0 to %T432 52 %r2 = sext %T416 %v1 to %T432 53 %r3 = mul %T432 %r1, %r2 54; ASM: vmull.s16 55 store %T432 %r3, %T432* %storeaddr 56; ASM: vst1.64 57 ret void 58} 59 60define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) { 61; COST-LABEL: 'upu1632' 62; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, <4 x i16>* %loadaddr, align 8 63; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, <4 x i16>* %loadaddr2, align 8 64; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext <4 x i16> %v0 to <4 x i32> 65; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = zext <4 x i16> %v1 to <4 x i32> 66; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %r1, %r2 67; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, <4 x i32>* %storeaddr, align 8 68; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void 69; 70 %v0 = load %T416, %T416* %loadaddr 71; ASM: vldr 72 %v1 = load %T416, %T416* %loadaddr2 73; ASM: vldr 74 %r1 = zext %T416 %v0 to %T432 75 %r2 = zext %T416 %v1 to %T432 76 %r3 = mul %T432 %r1, %r2 77; ASM: vmull.u16 78 store %T432 %r3, %T432* %storeaddr 79; ASM: vst1.64 80 ret void 81} 82 83define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) { 84; COST-LABEL: 'ups3264' 85; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, <2 x i32>* %loadaddr, align 8 86; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, <2 x i32>* %loadaddr2, align 8 87; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = mul <2 x i32> %v0, %v1 88; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = sext <2 x i32> %r3 to <2 x i64> 89; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, <2 x i64>* %storeaddr, align 8 90; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void 91; 92 %v0 = load %T232, %T232* %loadaddr 93; ASM: vldr 94 %v1 = load %T232, %T232* %loadaddr2 95; ASM: vldr 96 %r3 = mul %T232 %v0, %v1 97; ASM: vmul.i32 98 %st = sext %T232 %r3 to %T264 99; ASM: vmovl.s32 100 store %T264 %st, %T264* %storeaddr 101; ASM: vst1.64 102 ret void 103} 104 105define void @upu3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) { 106; COST-LABEL: 'upu3264' 107; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, <2 x i32>* %loadaddr, align 8 108; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, <2 x i32>* %loadaddr2, align 8 109; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = mul <2 x i32> %v0, %v1 110; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = zext <2 x i32> %r3 to <2 x i64> 111; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, <2 x i64>* %storeaddr, align 8 112; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void 113; 114 %v0 = load %T232, %T232* %loadaddr 115; ASM: vldr 116 %v1 = load %T232, %T232* %loadaddr2 117; ASM: vldr 118 %r3 = mul %T232 %v0, %v1 119; ASM: vmul.i32 120 %st = zext %T232 %r3 to %T264 121; ASM: vmovl.u32 122 store %T264 %st, %T264* %storeaddr 123; ASM: vst1.64 124 ret void 125} 126 127define void @dn3216(%T432* %loadaddr, %T432* %loadaddr2, %T416* %storeaddr) { 128; COST-LABEL: 'dn3216' 129; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, <4 x i32>* %loadaddr, align 8 130; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, <4 x i32>* %loadaddr2, align 8 131; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %v0, %v1 132; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = trunc <4 x i32> %r3 to <4 x i16> 133; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i16> %st, <4 x i16>* %storeaddr, align 8 134; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void 135; 136 %v0 = load %T432, %T432* %loadaddr 137; ASM: vld1.64 138 %v1 = load %T432, %T432* %loadaddr2 139; ASM: vld1.64 140 %r3 = mul %T432 %v0, %v1 141; ASM: vmul.i32 142 %st = trunc %T432 %r3 to %T416 143; ASM: vmovn.i32 144 store %T416 %st, %T416* %storeaddr 145; ASM: vstr 146 ret void 147} 148