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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dlsr.s10 lsr z0.b, z0.b, #1 label
16 lsr z31.b, z31.b, #8 label
22 lsr z0.h, z0.h, #1 label
28 lsr z31.h, z31.h, #16 label
34 lsr z0.s, z0.s, #1 label
40 lsr z31.s, z31.s, #32 label
46 lsr z0.d, z0.d, #1 label
52 lsr z31.d, z31.d, #64 label
58 lsr z0.b, p0/m, z0.b, #1 label
64 lsr z31.b, p0/m, z31.b, #8 label
[all …]
Dlsr-diagnostics.s3 lsr z30.b, z10.b, #0 label
8 lsr z18.b, z27.b, #9 label
13 lsr z18.b, p0/m, z28.b, #0 label
18 lsr z1.b, p0/m, z9.b, #9 label
23 lsr z26.h, z4.h, #0 label
28 lsr z25.h, z10.h, #17 label
33 lsr z21.h, p0/m, z2.h, #0 label
38 lsr z14.h, p0/m, z30.h, #17 label
43 lsr z17.s, z0.s, #0 label
48 lsr z0.s, z15.s, #33 label
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dremove_lsr.ll4 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
5 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
8 ; r17:16 = lsr(r11:10, #32)
11 ; r17:16 = lsr(r11:10, #32)
13 ; This makes the lsr instruction dead and it gets removed subsequently
32 %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
33 %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
34 %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
35 %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
36 %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dparity.ll8 ; CHECK-NEXT: eor r0, r0, r0, lsr #2
9 ; CHECK-NEXT: eor r0, r0, r0, lsr #1
21 ; CHECK-NEXT: eor r0, r0, r0, lsr #4
22 ; CHECK-NEXT: eor r0, r0, r0, lsr #2
23 ; CHECK-NEXT: eor r0, r0, r0, lsr #1
35 ; CHECK-NEXT: eor r0, r0, r0, lsr #8
36 ; CHECK-NEXT: eor r0, r0, r0, lsr #4
37 ; CHECK-NEXT: eor r0, r0, r0, lsr #2
38 ; CHECK-NEXT: eor r0, r0, r0, lsr #1
50 ; CHECK-NEXT: eor r0, r0, r0, lsr #16
[all …]
/external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/
Dlsr-postinc-pos-addrspace.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
10 ; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 2, %entry ]
11 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
12 ; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
13 ; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, -2
17 ; CHECK: inttoptr i32 %lsr.iv.next2 to i8 addrspace(3)*
41 ; CHECK: %lsr.iv1 = phi i64
42 ; CHECK: %lsr.iv = phi i64
43 ; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
44 ; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, -2
[all …]
/external/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/
Dlsr-postinc-pos-addrspace.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
10 ; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 2, %entry ]
11 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
12 ; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
13 ; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, -2
17 ; CHECK: inttoptr i32 %lsr.iv.next2 to i8 addrspace(3)*
41 ; CHECK: %lsr.iv1 = phi i64
42 ; CHECK: %lsr.iv = phi i64
43 ; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
44 ; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, -2
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dparity.ll8 ; CHECK-NEXT: eor w8, w8, w8, lsr #2
9 ; CHECK-NEXT: eor w8, w8, w8, lsr #1
21 ; CHECK-NEXT: eor w8, w8, w8, lsr #4
22 ; CHECK-NEXT: eor w8, w8, w8, lsr #2
23 ; CHECK-NEXT: eor w8, w8, w8, lsr #1
35 ; CHECK-NEXT: eor w8, w8, w8, lsr #8
36 ; CHECK-NEXT: eor w8, w8, w8, lsr #4
37 ; CHECK-NEXT: eor w8, w8, w8, lsr #2
38 ; CHECK-NEXT: eor w8, w8, w8, lsr #1
50 ; CHECK-NEXT: eor w8, w8, w8, lsr #16
[all …]
Durem-vector-lkk.ll15 ; CHECK-NEXT: lsr x11, x11, #37
21 ; CHECK-NEXT: lsr x9, x9, #34
27 ; CHECK-NEXT: lsr x9, x9, #32
29 ; CHECK-NEXT: add w9, w9, w11, lsr #1
31 ; CHECK-NEXT: lsr w9, w9, #6
40 ; CHECK-NEXT: lsr x9, x9, #40
61 ; CHECK-NEXT: lsr x13, x13, #32
64 ; CHECK-NEXT: lsr x14, x14, #32
67 ; CHECK-NEXT: lsr x15, x15, #32
68 ; CHECK-NEXT: add w13, w13, w16, lsr #1
[all …]
Darm64-popcnt.ll17 ; CHECK-NONEON-NEXT: lsr w8, w0, #1
21 ; CHECK-NONEON-NEXT: lsr w8, w8, #2
24 ; CHECK-NONEON-NEXT: add w8, w8, w8, lsr #4
28 ; CHECK-NONEON-NEXT: lsr w0, w8, #24
47 ; CHECK-NONEON-NEXT: lsr w8, w0, #1
51 ; CHECK-NONEON-NEXT: lsr w8, w8, #2
54 ; CHECK-NONEON-NEXT: add w8, w8, w8, lsr #4
58 ; CHECK-NONEON-NEXT: lsr w0, w8, #24
76 ; CHECK-NONEON-NEXT: lsr x8, x0, #1
80 ; CHECK-NONEON-NEXT: lsr x8, x8, #2
[all …]
/external/llvm-project/llvm/test/MC/AVR/
Dinst-lsr.s7 lsr r31
8 lsr r25
9 lsr r5
10 lsr r0
12 ; CHECK: lsr r31 ; encoding: [0xf6,0x95]
13 ; CHECK: lsr r25 ; encoding: [0x96,0x95]
14 ; CHECK: lsr r5 ; encoding: [0x56,0x94]
15 ; CHECK: lsr r0 ; encoding: [0x06,0x94]
17 ; CHECK-INST: lsr r31
18 ; CHECK-INST: lsr r25
[all …]
/external/icu/tools/cldr/cldr-to-icu/src/test/java/org/unicode/icu/tool/cldrtoicu/localedistance/
DLikelySubtagsBuilderTest.java14 import static org.unicode.icu.tool.cldrtoicu.localedistance.TestData.lsr;
75 lsr(""), in testLikelySubtags()
76 lsr("skip-script"), in testLikelySubtags()
78 lsr("en-Latn-US"), in testLikelySubtags()
79 lsr("pt-Latn-BR"), in testLikelySubtags()
80 lsr("zh-Hans-CN"), in testLikelySubtags()
81 lsr("zh-Hant-TW")) in testLikelySubtags()
89 "*-*-*", lsr("en-Latn-US"), in testLikelySubtags()
90 "*-*-BR", lsr("pt-Latn-BR"), in testLikelySubtags()
91 "*-Latn-*", lsr("en-Latn-US"), in testLikelySubtags()
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dtail-pred-const.ll43 %lsr.iv14 = phi i32* [ %scevgep15, %vector.body ], [ %A, %entry ]
44 %lsr.iv11 = phi i32* [ %scevgep12, %vector.body ], [ %C, %entry ]
45 %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %B, %entry ]
48 %lsr.iv1416 = bitcast i32* %lsr.iv14 to <4 x i32>*
49 %lsr.iv1113 = bitcast i32* %lsr.iv11 to <4 x i32>*
50 %lsr.iv10 = bitcast i32* %lsr.iv to <4 x i32>*
58 …%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv10, i32 4, <4…
59 …%wide.masked.load9 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1113, i32 4,…
61 …call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %2, <4 x i32>* %lsr.iv1416, i32 4, <4 x i1> %…
63 %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
[all …]
Dbranch-targets.ll34 %scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1
36 %scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1
39 %scevgep3 = getelementptr i32, i32* %lsr.iv1, i32 1
41 %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1
42 %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1
43 %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1
49 %lsr.iv9 = phi i32* [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ]
50 %lsr.iv5 = phi i32* [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]
51 %lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]
77 %scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1
[all …]
/external/llvm-project/llvm/test/CodeGen/AVR/
Dctlz.ll16 ; CHECK: lsr {{.*}}[[SCRATCH]]
19 ; CHECK: lsr {{.*}}[[RESULT]]
20 ; CHECK: lsr {{.*}}[[RESULT]]
23 ; CHECK: lsr {{.*}}[[SCRATCH]]
24 ; CHECK: lsr {{.*}}[[SCRATCH]]
25 ; CHECK: lsr {{.*}}[[SCRATCH]]
26 ; CHECK: lsr {{.*}}[[SCRATCH]]
30 ; CHECK: lsr {{.*}}[[RESULT]]
35 ; CHECK: lsr {{.*}}[[SCRATCH]]
36 ; CHECK: lsr {{.*}}[[SCRATCH]]
[all …]
/external/llvm-project/llvm/test/Analysis/BasicAA/
Dphi-spec-order.ll17 …%lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds (…
19 %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
21 ; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4
23 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
24 %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
25 %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
26 %scevgep11 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -2
29 store <4 x double> %add, <4 x double>* %lsr.iv12, align 32
30 %scevgep10 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -1
33 %scevgep9 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 1
[all …]
/external/llvm/test/Analysis/BasicAA/
Dphi-spec-order.ll17 …%lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds (…
19 %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
21 ; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4
23 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
24 %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
25 %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
26 %scevgep11 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -2
29 store <4 x double> %add, <4 x double>* %lsr.iv12, align 32
30 %scevgep10 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -1
33 %scevgep9 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 1
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dfast-isel-trunc-kill-subreg.ll21 %lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
22 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
23 %lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
24 %lsr.iv.next4 = add i64 %lsr.iv3, 32
25 %exitcond = icmp eq i32 %lsr.iv.next2, 8
33 %lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
34 %lsr.iv.next = add i32 %lsr.iv, 4
35 %tmp272 = icmp slt i32 %lsr.iv.next, 100
/external/llvm/test/CodeGen/X86/
Dfast-isel-trunc-kill-subreg.ll21 %lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
22 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
23 %lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
24 %lsr.iv.next4 = add i64 %lsr.iv3, 32
25 %exitcond = icmp eq i32 %lsr.iv.next2, 8
33 %lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
34 %lsr.iv.next = add i32 %lsr.iv, 4
35 %tmp272 = icmp slt i32 %lsr.iv.next, 100
/external/llvm-project/llvm/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
17 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
21 ldrt r1, [r0], r2, lsr #3
25 ldrbt r1, [r0], r2, lsr #3
29 strt r1, [r0], r2, lsr #3
33 strbt r1, [r0], r2, lsr #3
38 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
39 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
Darm-shift-encoding.s4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
34 @ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35 @ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
[all …]
/external/llvm/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
17 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
21 ldrt r1, [r0], r2, lsr #3
25 ldrbt r1, [r0], r2, lsr #3
29 strt r1, [r0], r2, lsr #3
33 strbt r1, [r0], r2, lsr #3
38 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
39 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
Darm-shift-encoding.s4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
34 @ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35 @ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dswp-carried-dep1.mir30 %lsr.iv7 = phi i16* [ %cgep9, %for.body.preheader ], [ %cgep12, %for.body ]
31 %lsr.iv2 = phi %struct.A* [ %scevgep1, %for.body.preheader ], [ %cgep11, %for.body ]
32 %lsr.iv = phi i32 [ %0, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
34 %lsr.iv24 = bitcast %struct.A* %lsr.iv2 to i16*
35 %1 = load i16, i16* %lsr.iv7, align 2
37 %cgep10 = getelementptr i16, i16* %lsr.iv24, i32 -4
41 store i16 %add, i16* %lsr.iv24, align 2
44 %lsr.iv.next = add i32 %lsr.iv, -1
45 %cmp = icmp eq i32 %lsr.iv.next, 0
46 %cgep11 = getelementptr %struct.A, %struct.A* %lsr.iv2, i32 1
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-logical-encoding.s54 and w1, w2, w3, lsr #2
55 and x1, x2, x3, lsr #2
65 ; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
66 ; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
76 ands w1, w2, w3, lsr #2
77 ands x1, x2, x3, lsr #2
87 ; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
88 ; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
98 bic w1, w2, w3, lsr #3
99 bic x1, x2, x3, lsr #3
[all …]
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s54 and w1, w2, w3, lsr #2
55 and x1, x2, x3, lsr #2
65 ; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
66 ; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
76 ands w1, w2, w3, lsr #2
77 ands x1, x2, x3, lsr #2
87 ; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
88 ; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
98 bic w1, w2, w3, lsr #3
99 bic x1, x2, x3, lsr #3
[all …]

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