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Searched refs:lsrl (Results 1 – 13 of 13) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-vmull-loop.ll20 ; CHECK-NEXT: lsrl r12, r5, #31
25 ; CHECK-NEXT: lsrl r12, r5, #31
31 ; CHECK-NEXT: lsrl r12, r5, #31
36 ; CHECK-NEXT: lsrl r12, r5, #31
Dshift_parts.ll107 ; CHECK-MVE-NEXT: lsrl r0, r1, #3
267 ; CHECK-MVE-NEXT: lsrl r0, r1, #3
284 ; CHECK-MVE-NEXT: lsrl r0, r1, #3
313 ; CHECK-MVE-NEXT: lsrl r0, r1, #31
330 ; CHECK-MVE-NEXT: lsrl r0, r1, #31
Dmve-postinc-distribute.ll100 ; CHECK-NEXT: lsrl r10, r5, #6
105 ; CHECK-NEXT: lsrl r6, r5, #6
121 ; CHECK-NEXT: lsrl r12, r7, #6
122 ; CHECK-NEXT: lsrl r4, r11, #6
Dmve-vqshrn.ll366 ; CHECK-NEXT: lsrl r0, r7, #3
380 ; CHECK-NEXT: lsrl r2, r3, #3
411 ; CHECK-NEXT: lsrl r0, r7, #3
425 ; CHECK-NEXT: lsrl r2, r3, #3
Dmve-shifts.ll257 ; CHECK-NEXT: lsrl r0, r1, #4
262 ; CHECK-NEXT: lsrl r0, r1, #4
Dmve-satmul-loops.ll785 ; CHECK-NEXT: lsrl r4, r5, #31
797 ; CHECK-NEXT: lsrl r6, r5, #31
826 ; CHECK-NEXT: lsrl r0, r1, #31
947 ; CHECK-NEXT: lsrl r4, r5, #31
961 ; CHECK-NEXT: lsrl r6, r5, #31
976 ; CHECK-NEXT: lsrl r4, r5, #31
989 ; CHECK-NEXT: lsrl r6, r5, #31
1017 ; CHECK-NEXT: lsrl r0, r1, #31
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dlongshift-demand.ll70 ; CHECK-NEXT: lsrl r0, r1, #3
151 ; CHECK-NEXT: lsrl r0, r1, #31
232 ; CHECK-NEXT: lsrl r0, r1, #32
409 ; CHECK-NEXT: lsrl r0, r1, #3
498 ; CHECK-NEXT: lsrl r0, r1, #31
587 ; CHECK-NEXT: lsrl r0, r1, #32
770 ; CHECK-NEXT: lsrl r0, r1, #3
859 ; CHECK-NEXT: lsrl r0, r1, #32
Dlongshift-const.ll323 ; CHECK-NEXT: lsrl r0, r1, #2
342 ; CHECK-NEXT: lsrl r0, r1, #32
/external/llvm-project/llvm/test/MC/ARM/
Dmve-scalar-shift.s102 # CHECK: lsrl lr, r1, #12 @ encoding: [0x5e,0xea,0x1f,0x31]
104 lsrl lr, r1, #12 label
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-scalar-shift.txt26 # CHECK: lsrl lr, r1, #12 @ encoding: [0x5e,0xea,0x1f,0x31]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td546 def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrMVE.td586 def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9891 "l\004lsll\003lsr\004lsrl\003mcr\004mcr2\004mcrr\005mcrr2\003mla\003mls\003"
10778 …{ 654 /* lsrl */, ARM::MVE_LSRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__Con…