1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @shl_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) { 5; CHECK-LABEL: shl_qq_int8_t: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vshl.u8 q0, q0, q1 8; CHECK-NEXT: bx lr 9entry: 10 %0 = shl <16 x i8> %src1, %src2 11 ret <16 x i8> %0 12} 13 14define arm_aapcs_vfpcc <8 x i16> @shl_qq_int16_t(<8 x i16> %src1, <8 x i16> %src2) { 15; CHECK-LABEL: shl_qq_int16_t: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: vshl.u16 q0, q0, q1 18; CHECK-NEXT: bx lr 19entry: 20 %0 = shl <8 x i16> %src1, %src2 21 ret <8 x i16> %0 22} 23 24define arm_aapcs_vfpcc <4 x i32> @shl_qq_int32_t(<4 x i32> %src1, <4 x i32> %src2) { 25; CHECK-LABEL: shl_qq_int32_t: 26; CHECK: @ %bb.0: @ %entry 27; CHECK-NEXT: vshl.u32 q0, q0, q1 28; CHECK-NEXT: bx lr 29entry: 30 %0 = shl <4 x i32> %src1, %src2 31 ret <4 x i32> %0 32} 33 34define arm_aapcs_vfpcc <2 x i64> @shl_qq_int64_t(<2 x i64> %src1, <2 x i64> %src2) { 35; CHECK-LABEL: shl_qq_int64_t: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: vmov r0, s4 38; CHECK-NEXT: vmov r1, s1 39; CHECK-NEXT: vmov r2, s0 40; CHECK-NEXT: lsll r2, r1, r0 41; CHECK-NEXT: vmov r0, s6 42; CHECK-NEXT: vmov.32 q2[0], r2 43; CHECK-NEXT: vmov r2, s2 44; CHECK-NEXT: vmov.32 q2[1], r1 45; CHECK-NEXT: vmov r1, s3 46; CHECK-NEXT: lsll r2, r1, r0 47; CHECK-NEXT: vmov.32 q2[2], r2 48; CHECK-NEXT: vmov.32 q2[3], r1 49; CHECK-NEXT: vmov q0, q2 50; CHECK-NEXT: bx lr 51entry: 52 %0 = shl <2 x i64> %src1, %src2 53 ret <2 x i64> %0 54} 55 56 57define arm_aapcs_vfpcc <16 x i8> @shru_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) { 58; CHECK-LABEL: shru_qq_int8_t: 59; CHECK: @ %bb.0: @ %entry 60; CHECK-NEXT: vneg.s8 q1, q1 61; CHECK-NEXT: vshl.u8 q0, q0, q1 62; CHECK-NEXT: bx lr 63entry: 64 %0 = lshr <16 x i8> %src1, %src2 65 ret <16 x i8> %0 66} 67 68define arm_aapcs_vfpcc <8 x i16> @shru_qq_int16_t(<8 x i16> %src1, <8 x i16> %src2) { 69; CHECK-LABEL: shru_qq_int16_t: 70; CHECK: @ %bb.0: @ %entry 71; CHECK-NEXT: vneg.s16 q1, q1 72; CHECK-NEXT: vshl.u16 q0, q0, q1 73; CHECK-NEXT: bx lr 74entry: 75 %0 = lshr <8 x i16> %src1, %src2 76 ret <8 x i16> %0 77} 78 79define arm_aapcs_vfpcc <4 x i32> @shru_qq_int32_t(<4 x i32> %src1, <4 x i32> %src2) { 80; CHECK-LABEL: shru_qq_int32_t: 81; CHECK: @ %bb.0: @ %entry 82; CHECK-NEXT: vneg.s32 q1, q1 83; CHECK-NEXT: vshl.u32 q0, q0, q1 84; CHECK-NEXT: bx lr 85entry: 86 %0 = lshr <4 x i32> %src1, %src2 87 ret <4 x i32> %0 88} 89 90define arm_aapcs_vfpcc <2 x i64> @shru_qq_int64_t(<2 x i64> %src1, <2 x i64> %src2) { 91; CHECK-LABEL: shru_qq_int64_t: 92; CHECK: @ %bb.0: @ %entry 93; CHECK-NEXT: vmov r2, s4 94; CHECK-NEXT: vmov r1, s1 95; CHECK-NEXT: vmov r0, s0 96; CHECK-NEXT: rsbs r2, r2, #0 97; CHECK-NEXT: lsll r0, r1, r2 98; CHECK-NEXT: vmov r2, s6 99; CHECK-NEXT: vmov.32 q2[0], r0 100; CHECK-NEXT: vmov r0, s2 101; CHECK-NEXT: vmov.32 q2[1], r1 102; CHECK-NEXT: vmov r1, s3 103; CHECK-NEXT: rsbs r2, r2, #0 104; CHECK-NEXT: lsll r0, r1, r2 105; CHECK-NEXT: vmov.32 q2[2], r0 106; CHECK-NEXT: vmov.32 q2[3], r1 107; CHECK-NEXT: vmov q0, q2 108; CHECK-NEXT: bx lr 109entry: 110 %0 = lshr <2 x i64> %src1, %src2 111 ret <2 x i64> %0 112} 113 114 115define arm_aapcs_vfpcc <16 x i8> @shrs_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) { 116; CHECK-LABEL: shrs_qq_int8_t: 117; CHECK: @ %bb.0: @ %entry 118; CHECK-NEXT: vneg.s8 q1, q1 119; CHECK-NEXT: vshl.s8 q0, q0, q1 120; CHECK-NEXT: bx lr 121entry: 122 %0 = ashr <16 x i8> %src1, %src2 123 ret <16 x i8> %0 124} 125 126define arm_aapcs_vfpcc <8 x i16> @shrs_qq_int16_t(<8 x i16> %src1, <8 x i16> %src2) { 127; CHECK-LABEL: shrs_qq_int16_t: 128; CHECK: @ %bb.0: @ %entry 129; CHECK-NEXT: vneg.s16 q1, q1 130; CHECK-NEXT: vshl.s16 q0, q0, q1 131; CHECK-NEXT: bx lr 132entry: 133 %0 = ashr <8 x i16> %src1, %src2 134 ret <8 x i16> %0 135} 136 137define arm_aapcs_vfpcc <4 x i32> @shrs_qq_int32_t(<4 x i32> %src1, <4 x i32> %src2) { 138; CHECK-LABEL: shrs_qq_int32_t: 139; CHECK: @ %bb.0: @ %entry 140; CHECK-NEXT: vneg.s32 q1, q1 141; CHECK-NEXT: vshl.s32 q0, q0, q1 142; CHECK-NEXT: bx lr 143entry: 144 %0 = ashr <4 x i32> %src1, %src2 145 ret <4 x i32> %0 146} 147 148define arm_aapcs_vfpcc <2 x i64> @shrs_qq_int64_t(<2 x i64> %src1, <2 x i64> %src2) { 149; CHECK-LABEL: shrs_qq_int64_t: 150; CHECK: @ %bb.0: @ %entry 151; CHECK-NEXT: vmov r0, s4 152; CHECK-NEXT: vmov r1, s1 153; CHECK-NEXT: vmov r2, s0 154; CHECK-NEXT: asrl r2, r1, r0 155; CHECK-NEXT: vmov r0, s6 156; CHECK-NEXT: vmov.32 q2[0], r2 157; CHECK-NEXT: vmov r2, s2 158; CHECK-NEXT: vmov.32 q2[1], r1 159; CHECK-NEXT: vmov r1, s3 160; CHECK-NEXT: asrl r2, r1, r0 161; CHECK-NEXT: vmov.32 q2[2], r2 162; CHECK-NEXT: vmov.32 q2[3], r1 163; CHECK-NEXT: vmov q0, q2 164; CHECK-NEXT: bx lr 165entry: 166 %0 = ashr <2 x i64> %src1, %src2 167 ret <2 x i64> %0 168} 169 170 171define arm_aapcs_vfpcc <16 x i8> @shl_qi_int8_t(<16 x i8> %src1) { 172; CHECK-LABEL: shl_qi_int8_t: 173; CHECK: @ %bb.0: @ %entry 174; CHECK-NEXT: vshl.i8 q0, q0, #4 175; CHECK-NEXT: bx lr 176entry: 177 %0 = shl <16 x i8> %src1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> 178 ret <16 x i8> %0 179} 180 181define arm_aapcs_vfpcc <8 x i16> @shl_qi_int16_t(<8 x i16> %src1) { 182; CHECK-LABEL: shl_qi_int16_t: 183; CHECK: @ %bb.0: @ %entry 184; CHECK-NEXT: vshl.i16 q0, q0, #4 185; CHECK-NEXT: bx lr 186entry: 187 %0 = shl <8 x i16> %src1, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> 188 ret <8 x i16> %0 189} 190 191define arm_aapcs_vfpcc <4 x i32> @shl_qi_int32_t(<4 x i32> %src1) { 192; CHECK-LABEL: shl_qi_int32_t: 193; CHECK: @ %bb.0: @ %entry 194; CHECK-NEXT: vshl.i32 q0, q0, #4 195; CHECK-NEXT: bx lr 196entry: 197 %0 = shl <4 x i32> %src1, <i32 4, i32 4, i32 4, i32 4> 198 ret <4 x i32> %0 199} 200 201define arm_aapcs_vfpcc <2 x i64> @shl_qi_int64_t(<2 x i64> %src1) { 202; CHECK-LABEL: shl_qi_int64_t: 203; CHECK: @ %bb.0: @ %entry 204; CHECK-NEXT: vmov r1, s1 205; CHECK-NEXT: vmov r0, s0 206; CHECK-NEXT: lsll r0, r1, #4 207; CHECK-NEXT: vmov.32 q1[0], r0 208; CHECK-NEXT: vmov r0, s2 209; CHECK-NEXT: vmov.32 q1[1], r1 210; CHECK-NEXT: vmov r1, s3 211; CHECK-NEXT: lsll r0, r1, #4 212; CHECK-NEXT: vmov.32 q1[2], r0 213; CHECK-NEXT: vmov.32 q1[3], r1 214; CHECK-NEXT: vmov q0, q1 215; CHECK-NEXT: bx lr 216entry: 217 %0 = shl <2 x i64> %src1, <i64 4, i64 4> 218 ret <2 x i64> %0 219} 220 221 222define arm_aapcs_vfpcc <16 x i8> @shru_qi_int8_t(<16 x i8> %src1) { 223; CHECK-LABEL: shru_qi_int8_t: 224; CHECK: @ %bb.0: @ %entry 225; CHECK-NEXT: vshr.u8 q0, q0, #4 226; CHECK-NEXT: bx lr 227entry: 228 %0 = lshr <16 x i8> %src1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> 229 ret <16 x i8> %0 230} 231 232define arm_aapcs_vfpcc <8 x i16> @shru_qi_int16_t(<8 x i16> %src1) { 233; CHECK-LABEL: shru_qi_int16_t: 234; CHECK: @ %bb.0: @ %entry 235; CHECK-NEXT: vshr.u16 q0, q0, #4 236; CHECK-NEXT: bx lr 237entry: 238 %0 = lshr <8 x i16> %src1, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> 239 ret <8 x i16> %0 240} 241 242define arm_aapcs_vfpcc <4 x i32> @shru_qi_int32_t(<4 x i32> %src1) { 243; CHECK-LABEL: shru_qi_int32_t: 244; CHECK: @ %bb.0: @ %entry 245; CHECK-NEXT: vshr.u32 q0, q0, #4 246; CHECK-NEXT: bx lr 247entry: 248 %0 = lshr <4 x i32> %src1, <i32 4, i32 4, i32 4, i32 4> 249 ret <4 x i32> %0 250} 251 252define arm_aapcs_vfpcc <2 x i64> @shru_qi_int64_t(<2 x i64> %src1) { 253; CHECK-LABEL: shru_qi_int64_t: 254; CHECK: @ %bb.0: @ %entry 255; CHECK-NEXT: vmov r1, s1 256; CHECK-NEXT: vmov r0, s0 257; CHECK-NEXT: lsrl r0, r1, #4 258; CHECK-NEXT: vmov.32 q1[0], r0 259; CHECK-NEXT: vmov r0, s2 260; CHECK-NEXT: vmov.32 q1[1], r1 261; CHECK-NEXT: vmov r1, s3 262; CHECK-NEXT: lsrl r0, r1, #4 263; CHECK-NEXT: vmov.32 q1[2], r0 264; CHECK-NEXT: vmov.32 q1[3], r1 265; CHECK-NEXT: vmov q0, q1 266; CHECK-NEXT: bx lr 267entry: 268 %0 = lshr <2 x i64> %src1, <i64 4, i64 4> 269 ret <2 x i64> %0 270} 271 272 273define arm_aapcs_vfpcc <16 x i8> @shrs_qi_int8_t(<16 x i8> %src1) { 274; CHECK-LABEL: shrs_qi_int8_t: 275; CHECK: @ %bb.0: @ %entry 276; CHECK-NEXT: vshr.s8 q0, q0, #4 277; CHECK-NEXT: bx lr 278entry: 279 %0 = ashr <16 x i8> %src1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> 280 ret <16 x i8> %0 281} 282 283define arm_aapcs_vfpcc <8 x i16> @shrs_qi_int16_t(<8 x i16> %src1) { 284; CHECK-LABEL: shrs_qi_int16_t: 285; CHECK: @ %bb.0: @ %entry 286; CHECK-NEXT: vshr.s16 q0, q0, #4 287; CHECK-NEXT: bx lr 288entry: 289 %0 = ashr <8 x i16> %src1, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> 290 ret <8 x i16> %0 291} 292 293define arm_aapcs_vfpcc <4 x i32> @shrs_qi_int32_t(<4 x i32> %src1) { 294; CHECK-LABEL: shrs_qi_int32_t: 295; CHECK: @ %bb.0: @ %entry 296; CHECK-NEXT: vshr.s32 q0, q0, #4 297; CHECK-NEXT: bx lr 298entry: 299 %0 = ashr <4 x i32> %src1, <i32 4, i32 4, i32 4, i32 4> 300 ret <4 x i32> %0 301} 302 303define arm_aapcs_vfpcc <2 x i64> @shrs_qi_int64_t(<2 x i64> %src1) { 304; CHECK-LABEL: shrs_qi_int64_t: 305; CHECK: @ %bb.0: @ %entry 306; CHECK-NEXT: vmov r1, s1 307; CHECK-NEXT: vmov r0, s0 308; CHECK-NEXT: asrl r0, r1, #4 309; CHECK-NEXT: vmov.32 q1[0], r0 310; CHECK-NEXT: vmov r0, s2 311; CHECK-NEXT: vmov.32 q1[1], r1 312; CHECK-NEXT: vmov r1, s3 313; CHECK-NEXT: asrl r0, r1, #4 314; CHECK-NEXT: vmov.32 q1[2], r0 315; CHECK-NEXT: vmov.32 q1[3], r1 316; CHECK-NEXT: vmov q0, q1 317; CHECK-NEXT: bx lr 318entry: 319 %0 = ashr <2 x i64> %src1, <i64 4, i64 4> 320 ret <2 x i64> %0 321} 322 323 324define arm_aapcs_vfpcc <16 x i8> @shl_qr_int8_t(<16 x i8> %src1, i8 %src2) { 325; CHECK-LABEL: shl_qr_int8_t: 326; CHECK: @ %bb.0: @ %entry 327; CHECK-NEXT: vshl.u8 q0, r0 328; CHECK-NEXT: bx lr 329entry: 330 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 331 %s = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 332 %0 = shl <16 x i8> %src1, %s 333 ret <16 x i8> %0 334} 335 336define arm_aapcs_vfpcc <8 x i16> @shl_qr_int16_t(<8 x i16> %src1, i16 %src2) { 337; CHECK-LABEL: shl_qr_int16_t: 338; CHECK: @ %bb.0: @ %entry 339; CHECK-NEXT: vshl.u16 q0, r0 340; CHECK-NEXT: bx lr 341entry: 342 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 343 %s = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 344 %0 = shl <8 x i16> %src1, %s 345 ret <8 x i16> %0 346} 347 348define arm_aapcs_vfpcc <4 x i32> @shl_qr_int32_t(<4 x i32> %src1, i32 %src2) { 349; CHECK-LABEL: shl_qr_int32_t: 350; CHECK: @ %bb.0: @ %entry 351; CHECK-NEXT: vshl.u32 q0, r0 352; CHECK-NEXT: bx lr 353entry: 354 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 355 %s = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 356 %0 = shl <4 x i32> %src1, %s 357 ret <4 x i32> %0 358} 359 360define arm_aapcs_vfpcc <2 x i64> @shl_qr_int64_t(<2 x i64> %src1, i64 %src2) { 361; CHECK-LABEL: shl_qr_int64_t: 362; CHECK: @ %bb.0: @ %entry 363; CHECK-NEXT: vmov r1, s1 364; CHECK-NEXT: vmov r2, s0 365; CHECK-NEXT: lsll r2, r1, r0 366; CHECK-NEXT: vmov.32 q1[0], r2 367; CHECK-NEXT: vmov r2, s2 368; CHECK-NEXT: vmov.32 q1[1], r1 369; CHECK-NEXT: vmov r1, s3 370; CHECK-NEXT: lsll r2, r1, r0 371; CHECK-NEXT: vmov.32 q1[2], r2 372; CHECK-NEXT: vmov.32 q1[3], r1 373; CHECK-NEXT: vmov q0, q1 374; CHECK-NEXT: bx lr 375entry: 376 %i = insertelement <2 x i64> undef, i64 %src2, i32 0 377 %s = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 378 %0 = shl <2 x i64> %src1, %s 379 ret <2 x i64> %0 380} 381 382 383define arm_aapcs_vfpcc <16 x i8> @shru_qr_int8_t(<16 x i8> %src1, i8 %src2) { 384; CHECK-LABEL: shru_qr_int8_t: 385; CHECK: @ %bb.0: @ %entry 386; CHECK-NEXT: rsbs r0, r0, #0 387; CHECK-NEXT: vshl.u8 q0, r0 388; CHECK-NEXT: bx lr 389entry: 390 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 391 %s = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 392 %0 = lshr <16 x i8> %src1, %s 393 ret <16 x i8> %0 394} 395 396define arm_aapcs_vfpcc <8 x i16> @shru_qr_int16_t(<8 x i16> %src1, i16 %src2) { 397; CHECK-LABEL: shru_qr_int16_t: 398; CHECK: @ %bb.0: @ %entry 399; CHECK-NEXT: rsbs r0, r0, #0 400; CHECK-NEXT: vshl.u16 q0, r0 401; CHECK-NEXT: bx lr 402entry: 403 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 404 %s = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 405 %0 = lshr <8 x i16> %src1, %s 406 ret <8 x i16> %0 407} 408 409define arm_aapcs_vfpcc <4 x i32> @shru_qr_int32_t(<4 x i32> %src1, i32 %src2) { 410; CHECK-LABEL: shru_qr_int32_t: 411; CHECK: @ %bb.0: @ %entry 412; CHECK-NEXT: rsbs r0, r0, #0 413; CHECK-NEXT: vshl.u32 q0, r0 414; CHECK-NEXT: bx lr 415entry: 416 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 417 %s = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 418 %0 = lshr <4 x i32> %src1, %s 419 ret <4 x i32> %0 420} 421 422define arm_aapcs_vfpcc <2 x i64> @shru_qr_int64_t(<2 x i64> %src1, i64 %src2) { 423; CHECK-LABEL: shru_qr_int64_t: 424; CHECK: @ %bb.0: @ %entry 425; CHECK-NEXT: rsbs r0, r0, #0 426; CHECK-NEXT: vmov r1, s1 427; CHECK-NEXT: vmov r2, s0 428; CHECK-NEXT: lsll r2, r1, r0 429; CHECK-NEXT: vmov.32 q1[0], r2 430; CHECK-NEXT: vmov r2, s2 431; CHECK-NEXT: vmov.32 q1[1], r1 432; CHECK-NEXT: vmov r1, s3 433; CHECK-NEXT: lsll r2, r1, r0 434; CHECK-NEXT: vmov.32 q1[2], r2 435; CHECK-NEXT: vmov.32 q1[3], r1 436; CHECK-NEXT: vmov q0, q1 437; CHECK-NEXT: bx lr 438entry: 439 %i = insertelement <2 x i64> undef, i64 %src2, i32 0 440 %s = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 441 %0 = lshr <2 x i64> %src1, %s 442 ret <2 x i64> %0 443} 444 445 446define arm_aapcs_vfpcc <16 x i8> @shrs_qr_int8_t(<16 x i8> %src1, i8 %src2) { 447; CHECK-LABEL: shrs_qr_int8_t: 448; CHECK: @ %bb.0: @ %entry 449; CHECK-NEXT: rsbs r0, r0, #0 450; CHECK-NEXT: vshl.s8 q0, r0 451; CHECK-NEXT: bx lr 452entry: 453 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 454 %s = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 455 %0 = ashr <16 x i8> %src1, %s 456 ret <16 x i8> %0 457} 458 459define arm_aapcs_vfpcc <8 x i16> @shrs_qr_int16_t(<8 x i16> %src1, i16 %src2) { 460; CHECK-LABEL: shrs_qr_int16_t: 461; CHECK: @ %bb.0: @ %entry 462; CHECK-NEXT: rsbs r0, r0, #0 463; CHECK-NEXT: vshl.s16 q0, r0 464; CHECK-NEXT: bx lr 465entry: 466 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 467 %s = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 468 %0 = ashr <8 x i16> %src1, %s 469 ret <8 x i16> %0 470} 471 472define arm_aapcs_vfpcc <4 x i32> @shrs_qr_int32_t(<4 x i32> %src1, i32 %src2) { 473; CHECK-LABEL: shrs_qr_int32_t: 474; CHECK: @ %bb.0: @ %entry 475; CHECK-NEXT: rsbs r0, r0, #0 476; CHECK-NEXT: vshl.s32 q0, r0 477; CHECK-NEXT: bx lr 478entry: 479 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 480 %s = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 481 %0 = ashr <4 x i32> %src1, %s 482 ret <4 x i32> %0 483} 484 485define arm_aapcs_vfpcc <2 x i64> @shrs_qr_int64_t(<2 x i64> %src1, i64 %src2) { 486; CHECK-LABEL: shrs_qr_int64_t: 487; CHECK: @ %bb.0: @ %entry 488; CHECK-NEXT: vmov r1, s1 489; CHECK-NEXT: vmov r2, s0 490; CHECK-NEXT: asrl r2, r1, r0 491; CHECK-NEXT: vmov.32 q1[0], r2 492; CHECK-NEXT: vmov r2, s2 493; CHECK-NEXT: vmov.32 q1[1], r1 494; CHECK-NEXT: vmov r1, s3 495; CHECK-NEXT: asrl r2, r1, r0 496; CHECK-NEXT: vmov.32 q1[2], r2 497; CHECK-NEXT: vmov.32 q1[3], r1 498; CHECK-NEXT: vmov q0, q1 499; CHECK-NEXT: bx lr 500entry: 501 %i = insertelement <2 x i64> undef, i64 %src2, i32 0 502 %s = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 503 %0 = ashr <2 x i64> %src1, %s 504 ret <2 x i64> %0 505} 506 507define arm_aapcs_vfpcc <16 x i8> @shl_qiv_int8_t(<16 x i8> %src1) { 508; CHECK-LABEL: shl_qiv_int8_t: 509; CHECK: @ %bb.0: @ %entry 510; CHECK-NEXT: adr r0, .LCPI36_0 511; CHECK-NEXT: vldrw.u32 q1, [r0] 512; CHECK-NEXT: vshl.u8 q0, q0, q1 513; CHECK-NEXT: bx lr 514; CHECK-NEXT: .p2align 4 515; CHECK-NEXT: @ %bb.1: 516; CHECK-NEXT: .LCPI36_0: 517; CHECK-NEXT: .byte 1 @ 0x1 518; CHECK-NEXT: .byte 2 @ 0x2 519; CHECK-NEXT: .byte 3 @ 0x3 520; CHECK-NEXT: .byte 4 @ 0x4 521; CHECK-NEXT: .byte 1 @ 0x1 522; CHECK-NEXT: .byte 2 @ 0x2 523; CHECK-NEXT: .byte 3 @ 0x3 524; CHECK-NEXT: .byte 4 @ 0x4 525; CHECK-NEXT: .byte 1 @ 0x1 526; CHECK-NEXT: .byte 2 @ 0x2 527; CHECK-NEXT: .byte 3 @ 0x3 528; CHECK-NEXT: .byte 4 @ 0x4 529; CHECK-NEXT: .byte 1 @ 0x1 530; CHECK-NEXT: .byte 2 @ 0x2 531; CHECK-NEXT: .byte 3 @ 0x3 532; CHECK-NEXT: .byte 4 @ 0x4 533entry: 534 %0 = shl <16 x i8> %src1, <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4> 535 ret <16 x i8> %0 536} 537 538define arm_aapcs_vfpcc <8 x i16> @shl_qiv_int16_t(<8 x i16> %src1) { 539; CHECK-LABEL: shl_qiv_int16_t: 540; CHECK: @ %bb.0: @ %entry 541; CHECK-NEXT: adr r0, .LCPI37_0 542; CHECK-NEXT: vldrw.u32 q1, [r0] 543; CHECK-NEXT: vshl.u16 q0, q0, q1 544; CHECK-NEXT: bx lr 545; CHECK-NEXT: .p2align 4 546; CHECK-NEXT: @ %bb.1: 547; CHECK-NEXT: .LCPI37_0: 548; CHECK-NEXT: .short 1 @ 0x1 549; CHECK-NEXT: .short 2 @ 0x2 550; CHECK-NEXT: .short 3 @ 0x3 551; CHECK-NEXT: .short 4 @ 0x4 552; CHECK-NEXT: .short 1 @ 0x1 553; CHECK-NEXT: .short 2 @ 0x2 554; CHECK-NEXT: .short 3 @ 0x3 555; CHECK-NEXT: .short 4 @ 0x4 556entry: 557 %0 = shl <8 x i16> %src1, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4> 558 ret <8 x i16> %0 559} 560 561define arm_aapcs_vfpcc <4 x i32> @shl_qiv_int32_t(<4 x i32> %src1) { 562; CHECK-LABEL: shl_qiv_int32_t: 563; CHECK: @ %bb.0: @ %entry 564; CHECK-NEXT: adr r0, .LCPI38_0 565; CHECK-NEXT: vldrw.u32 q1, [r0] 566; CHECK-NEXT: vshl.u32 q0, q0, q1 567; CHECK-NEXT: bx lr 568; CHECK-NEXT: .p2align 4 569; CHECK-NEXT: @ %bb.1: 570; CHECK-NEXT: .LCPI38_0: 571; CHECK-NEXT: .long 1 @ 0x1 572; CHECK-NEXT: .long 2 @ 0x2 573; CHECK-NEXT: .long 3 @ 0x3 574; CHECK-NEXT: .long 4 @ 0x4 575entry: 576 %0 = shl <4 x i32> %src1, <i32 1, i32 2, i32 3, i32 4> 577 ret <4 x i32> %0 578} 579