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Searched refs:meminfo_t (Results 1 – 25 of 40) sorted by relevance

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/external/arm-trusted-firmware/plat/arm/board/fvp/
Dfvp_bl1_setup.c87 meminfo_t *bl2_tzram_layout; in bl1_plat_handle_post_image_load()
88 meminfo_t *bl1_tzram_layout; in bl1_plat_handle_post_image_load()
116 bl2_tzram_layout = (meminfo_t *)bl1_tzram_layout->total_base; in bl1_plat_handle_post_image_load()
/external/arm-trusted-firmware/plat/common/
Dplat_bl1_common.c86 meminfo_t *bl2_secram_layout; in bl1_plat_handle_post_image_load()
87 meminfo_t *bl1_secram_layout; in bl1_plat_handle_post_image_load()
111 bl2_secram_layout = (meminfo_t *) bl1_secram_layout->total_base; in bl1_plat_handle_post_image_load()
/external/arm-trusted-firmware/plat/hisilicon/poplar/
Dbl1_plat_setup.c29 static meminfo_t bl1_tzram_layout;
30 static meminfo_t bl2_tzram_layout;
55 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); in bl1_plat_handle_post_image_load()
/external/arm-trusted-firmware/plat/rpi/rpi3/
Drpi3_bl2_setup.c25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
51 meminfo_t *mem_layout = (meminfo_t *) arg1; in bl2_early_platform_setup2()
Drpi3_bl1_setup.c20 static meminfo_t bl1_tzram_layout;
22 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
/external/arm-trusted-firmware/plat/marvell/armada/common/
Dmarvell_bl2_setup.c27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
35 meminfo_t *bl2_plat_sec_mem_layout(void) in bl2_plat_sec_mem_layout()
46 void marvell_bl2_early_platform_setup(meminfo_t *mem_layout) in marvell_bl2_early_platform_setup()
Dmarvell_bl1_setup.c26 static meminfo_t bl1_ram_layout;
28 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
/external/arm-trusted-firmware/plat/brcm/common/
Dbrcm_bl2_setup.c22 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
48 meminfo_t *mem_layout) in bcm_bl2_early_platform_setup()
75 bcm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/external/arm-trusted-firmware/plat/qemu/common/
Dqemu_bl1_setup.c18 static meminfo_t bl1_tzram_layout;
21 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
Dqemu_bl2_setup.c27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
32 meminfo_t *mem_layout = (void *)arg1; in bl2_early_platform_setup2()
/external/arm-trusted-firmware/plat/layerscape/common/
Dls_bl1_setup.c14 static meminfo_t bl1_tzram_layout;
16 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
Dls_bl2_setup.c17 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
24 void ls_bl2_early_platform_setup(meminfo_t *mem_layout) in ls_bl2_early_platform_setup()
/external/arm-trusted-firmware/bl1/
Dbl1_main.c37 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, in bl1_calc_bl2_mem_layout()
38 meminfo_t *bl2_mem_layout) in bl1_calc_bl2_mem_layout()
51 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); in bl1_calc_bl2_mem_layout()
/external/arm-trusted-firmware/include/bl1/
Dbl1.h98 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
99 meminfo_t *bl2_mem_layout);
/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_bl1_setup.c28 static meminfo_t bl1_tzram_layout;
37 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
/external/arm-trusted-firmware/plat/arm/common/
Darm_bl2_setup.c27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
77 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
Darm_bl2_el3_setup.c23 static meminfo_t bl2_el3_tzram_layout;
/external/arm-trusted-firmware/plat/layerscape/board/ls1043/
Dls1043_bl2_setup.c15 ls_bl2_early_platform_setup((meminfo_t *)arg1); in bl2_early_platform_setup2()
/external/arm-trusted-firmware/plat/arm/board/a5ds/
Da5ds_bl2_setup.c12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c43 static meminfo_t bl1_tzram_layout;
64 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
/external/arm-trusted-firmware/plat/arm/board/fvp_ve/
Dfvp_ve_bl2_setup.c18 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/external/arm-trusted-firmware/plat/arm/css/common/
Dcss_bl2u_setup.c25 void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) in bl2u_early_platform_setup()
Dcss_bl2_setup.c59 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/external/arm-trusted-firmware/plat/layerscape/common/include/
Dplat_ls.h19 void ls_bl2_early_platform_setup(meminfo_t *mem_layout);
/external/arm-trusted-firmware/include/plat/marvell/armada/a3k/common/
Dplat_marvell.h64 void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);

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