/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/ |
D | mtspmc.c | 45 mmio_clrbits_32(reg, SW_NO_WAIT_Q); in spm_enable_cpu_auto_off() 58 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); in spm_set_cpu_power_off() 65 mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q); in spm_enable_cluster_auto_off() 66 mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0)); in spm_enable_cluster_auto_off() 68 mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN); in spm_enable_cluster_auto_off() 70 mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON); in spm_enable_cluster_auto_off() 168 mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init() 170 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init() 171 mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init() 172 mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init() [all …]
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/external/arm-trusted-firmware/plat/allwinner/sun50i_a64/ |
D | sunxi_power.c | 45 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc() 46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc() 52 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc() 60 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); in sunxi_turn_off_soc() 61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); in sunxi_turn_off_soc() 75 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); in sunxi_turn_off_soc() 78 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); in sunxi_turn_off_soc() 81 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); in sunxi_turn_off_soc() 82 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); in sunxi_turn_off_soc()
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/external/arm-trusted-firmware/plat/imx/imx8m/ |
D | gpc_common.c | 60 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_on() 65 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on() 76 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on() 93 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm() 96 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm() 117 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config() 118 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config() 121 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config() 134 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby() 164 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); in imx_set_cluster_powerdown() [all …]
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/external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/ |
D | s10_memory_controller.c | 160 mmio_clrbits_32(S10_CCU_CPU0_MPRT_DDR, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 161 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 162 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 163 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 164 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 165 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 166 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 168 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 169 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() 170 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller() [all …]
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/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/ |
D | gpc.c | 47 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm() 69 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); in imx_pup_pdn_slot_config() 70 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); in imx_pup_pdn_slot_config() 71 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF); in imx_pup_pdn_slot_config() 104 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown() 115 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK); in imx_set_cluster_powerdown() 169 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK); in imx_gpc_init() 176 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init() 177 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
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/external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/spmc/ |
D | mtspmc.c | 25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup() 53 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate() 109 mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); in spmc_init() 110 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init() 111 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init() 137 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN); in spm_poweron_cpu() 141 mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3)); in spm_poweron_cpu() 154 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
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/external/arm-trusted-firmware/drivers/brcm/ |
D | sotp.c | 84 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_read() 106 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_read() 124 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_read() 177 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write() 185 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write() 216 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write() 248 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write() 252 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
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/external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
D | hikey960_bl1_setup.c | 114 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset() 119 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset() 120 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset() 146 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset() 152 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset() 153 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset() 154 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
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D | hikey960_bl2_setup.c | 89 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset() 94 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset() 95 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset() 121 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset() 127 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset() 128 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset() 129 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
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/external/arm-trusted-firmware/plat/allwinner/common/ |
D | sunxi_cpu_ops.c | 56 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_off() 65 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_off() 92 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on() 94 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on() 100 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); in sunxi_cpu_on()
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/external/arm-trusted-firmware/plat/intel/soc/common/soc/ |
D | socfpga_reset_manager.c | 18 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST), in deassert_peripheral_reset() 37 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset() 47 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset() 71 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), in deassert_peripheral_reset() 108 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); in socfpga_bridges_enable() 143 mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
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/external/arm-trusted-firmware/drivers/st/gpio/ |
D | stm32_gpio.c | 213 mmio_clrbits_32(base + GPIO_MODE_OFFSET, in set_gpio() 221 mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); in set_gpio() 224 mmio_clrbits_32(base + GPIO_SPEED_OFFSET, in set_gpio() 228 mmio_clrbits_32(base + GPIO_PUPD_OFFSET, in set_gpio() 233 mmio_clrbits_32(base + GPIO_AFRL_OFFSET, in set_gpio() 238 mmio_clrbits_32(base + GPIO_AFRH_OFFSET, in set_gpio() 281 mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); in set_gpio_secure_cfg()
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/external/arm-trusted-firmware/drivers/st/ddr/ |
D | stm32mp1_ddr.c | 387 mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in stm32mp1_start_sw_done() 631 mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off() 650 mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off() 666 mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off() 678 mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); in stm32mp1_refresh_disable() 679 mmio_clrbits_32((uintptr_t)&ctl->dfimisc, in stm32mp1_refresh_disable() 689 mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, in stm32mp1_refresh_restore() 756 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init() 757 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init() 762 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init() [all …]
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/external/arm-trusted-firmware/plat/brcm/board/stingray/src/ |
D | bl31_setup.c | 100 mmio_clrbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1); in brcm_stingray_dma_pl330_init() 115 mmio_clrbits_32(idm_reset_control, 0x1); in brcm_stingray_spi_pl022_init() 211 mmio_clrbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N); in brcm_stingray_sata_init() 235 mmio_clrbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init() 238 mmio_clrbits_32(SATA_PORT_REG(sata_port, in brcm_stingray_sata_init() 268 mmio_clrbits_32(CRMU_AON_CTRL1, in poweroff_sata_pll() 323 mmio_clrbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_ISO); in brcm_stingray_amac_init() 383 mmio_clrbits_32(icfg_mem_ctrl, ICFG_PKA_MEM_PWR_CTRL__ISO); in brcm_stingray_pka_meminit() 465 mmio_clrbits_32(icfg_mem_ctrl, ICFG_DMAC_MEM_PWR_CTRL__ISO); in brcm_stingray_dma_pl330_meminit() 523 mmio_clrbits_32(scr_base + 0x14, clr_mask); in brcm_stingray_scr_init() [all …]
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/external/arm-trusted-firmware/plat/intel/soc/common/drivers/ccu/ |
D | ncore_ccu.c | 100 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1), in bypass_ocram_firewall() 102 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2), in bypass_ocram_firewall() 104 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3), in bypass_ocram_firewall() 106 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4), in bypass_ocram_firewall()
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/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/ |
D | mtcmos.c | 138 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); in mtcmos_ctrl_little_off() 144 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); in mtcmos_ctrl_little_off() 146 mmio_clrbits_32(reg_pwr_con, PWR_ON); in mtcmos_ctrl_little_off() 147 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); in mtcmos_ctrl_little_off() 270 mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()
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/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/ |
D | mtgpio.c | 229 mmio_clrbits_32(pupd_addr, 3U << pupd_offset); in mt_set_gpio_pull_enable_chip() 231 mmio_clrbits_32(pullen_addr, in mt_set_gpio_pull_enable_chip() 242 mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1)); in mt_set_gpio_pull_enable_chip() 251 mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1)); in mt_set_gpio_pull_enable_chip() 255 mmio_clrbits_32(pupd_addr, 1U << pupd_offset); in mt_set_gpio_pull_enable_chip() 304 mmio_clrbits_32(pullsel_addr, in mt_set_gpio_pull_select_chip() 309 mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 2)); in mt_set_gpio_pull_select_chip() 318 mmio_clrbits_32(pullsel_addr, in mt_set_gpio_pull_select_chip()
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/external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/ |
D | gpc.c | 44 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | in imx_gpc_init() 86 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init() 87 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
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/external/arm-trusted-firmware/plat/marvell/armada/a3k/common/ |
D | plat_pm.c | 270 mmio_clrbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on() 313 mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_CPU_VDDV_OFF_EN); in a3700_set_gen_pwr_off_option() 324 mmio_clrbits_32(MVEBU_NB_CLOCK_SEL_REG, MVEBU_A53_CPU_CLK_SEL); in a3700_set_gen_pwr_off_option() 415 mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_AVS_DISABLE_MODE); in a3700_pwr_dn_avs() 494 mmio_clrbits_32(MVEBU_NB_GPIO_IRQ_MASK_2_REG, BIT(gpio - 32)); in a3700_pm_en_nb_gpio() 500 mmio_clrbits_32(MVEBU_NB_GPIO_IRQ_MASK_1_REG, BIT(gpio)); in a3700_pm_en_nb_gpio() 529 mmio_clrbits_32(MVEBU_SB_GPIO_IRQ_MASK_REG, BIT(gpio)); in a3700_pm_en_sb_gpio() 548 mmio_clrbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_UART1_SEL); in a3700_pm_src_uart1() 619 mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, in a3700_pm_clear_lp_flag()
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/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/ |
D | dram.c | 31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port() 77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main() 78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
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D | suspend.c | 27 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in m0_main() 55 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
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/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/ |
D | spm_suspend.c | 285 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); in bigcore_pll_on() 291 mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); in bigcore_pll_off() 293 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); in bigcore_pll_off()
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/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
D | suspend.c | 257 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); in data_training() 303 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); in data_training() 351 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); in data_training() 384 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); in data_training() 398 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); in data_training() 419 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); in data_training() 423 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training() 615 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start() 634 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start() 684 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, PMU_CLR_ALIVE); in pmusram_enable_watchdog()
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/external/arm-trusted-firmware/plat/mediatek/mt8173/ |
D | scu.c | 25 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, in enable_scu() 28 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, in enable_scu()
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/external/arm-trusted-firmware/plat/mediatek/mt6795/ |
D | scu.c | 25 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, in enable_scu() 28 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, in enable_scu()
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