1 /*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <errno.h>
9
10 #include <platform_def.h>
11
12 #include <common/debug.h>
13 #include <drivers/allwinner/axp.h>
14 #include <drivers/allwinner/sunxi_rsb.h>
15 #include <lib/mmio.h>
16
17 #include <sunxi_def.h>
18 #include <sunxi_mmap.h>
19 #include <sunxi_private.h>
20
21 static enum pmic_type {
22 UNKNOWN,
23 GENERIC_H5,
24 GENERIC_A64,
25 REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */
26 AXP803_RSB, /* PMIC connected via RSB on most A64 boards */
27 } pmic;
28
29 #define AXP803_HW_ADDR 0x3a3
30 #define AXP803_RT_ADDR 0x2d
31
32 /*
33 * On boards without a proper PMIC we struggle to turn off the system properly.
34 * Try to turn off as much off the system as we can, to reduce power
35 * consumption. This should be entered with only one core running and SMP
36 * disabled.
37 * This function only cares about peripherals.
38 */
sunxi_turn_off_soc(uint16_t socid)39 static void sunxi_turn_off_soc(uint16_t socid)
40 {
41 int i;
42
43 /** Turn off most peripherals, most importantly DRAM users. **/
44 /* Keep DRAM controller running for now. */
45 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14));
46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14));
47 /* Contains msgbox (bit 21) and spinlock (bit 22) */
48 mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0);
49 mmio_write_32(SUNXI_CCU_BASE + 0x64, 0);
50 mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0);
51 /* Keep PIO controller running for now. */
52 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5)));
53 mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0);
54 /* Contains UART0 (bit 16) */
55 mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0);
56 mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0);
57 mmio_write_32(SUNXI_CCU_BASE + 0x70, 0);
58
59 /** Turn off DRAM controller. **/
60 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14));
61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14));
62
63 /** Migrate CPU and bus clocks away from the PLLs. **/
64 /* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */
65 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000);
66 /* APB2: use OSC24M */
67 mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000);
68 /* AHB2: use AHB1 clock */
69 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0);
70 /* CPU: use OSC24M */
71 mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000);
72
73 /** Turn off PLLs. **/
74 for (i = 0; i < 6; i++)
75 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31));
76 switch (socid) {
77 case SUNXI_SOC_H5:
78 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31));
79 break;
80 case SUNXI_SOC_A64:
81 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31));
82 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31));
83 break;
84 }
85 }
86
rsb_init(void)87 static int rsb_init(void)
88 {
89 int ret;
90
91 ret = rsb_init_controller();
92 if (ret)
93 return ret;
94
95 /* Switch to the recommended 3 MHz bus clock. */
96 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
97 if (ret)
98 return ret;
99
100 /* Initiate an I2C transaction to switch the PMIC to RSB mode. */
101 ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
102 if (ret)
103 return ret;
104
105 /* Associate the 8-bit runtime address with the 12-bit bus address. */
106 ret = rsb_assign_runtime_address(AXP803_HW_ADDR,
107 AXP803_RT_ADDR);
108 if (ret)
109 return ret;
110
111 return axp_check_id();
112 }
113
axp_read(uint8_t reg)114 int axp_read(uint8_t reg)
115 {
116 return rsb_read(AXP803_RT_ADDR, reg);
117 }
118
axp_write(uint8_t reg,uint8_t val)119 int axp_write(uint8_t reg, uint8_t val)
120 {
121 return rsb_write(AXP803_RT_ADDR, reg, val);
122 }
123
sunxi_pmic_setup(uint16_t socid,const void * fdt)124 int sunxi_pmic_setup(uint16_t socid, const void *fdt)
125 {
126 int ret;
127
128 switch (socid) {
129 case SUNXI_SOC_H5:
130 NOTICE("PMIC: Assuming H5 reference regulator design\n");
131
132 pmic = REF_DESIGN_H5;
133
134 break;
135 case SUNXI_SOC_A64:
136 pmic = GENERIC_A64;
137
138 INFO("PMIC: Probing AXP803 on RSB\n");
139
140 ret = sunxi_init_platform_r_twi(socid, true);
141 if (ret)
142 return ret;
143
144 ret = rsb_init();
145 if (ret)
146 return ret;
147
148 pmic = AXP803_RSB;
149 axp_setup_regulators(fdt);
150
151 /* Switch the PMIC back to I2C mode. */
152 ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
153 if (ret)
154 return ret;
155
156 break;
157 default:
158 return -ENODEV;
159 }
160 return 0;
161 }
162
sunxi_power_down(void)163 void sunxi_power_down(void)
164 {
165 switch (pmic) {
166 case GENERIC_H5:
167 /* Turn off as many peripherals and clocks as we can. */
168 sunxi_turn_off_soc(SUNXI_SOC_H5);
169 /* Turn off the pin controller now. */
170 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
171 break;
172 case GENERIC_A64:
173 /* Turn off as many peripherals and clocks as we can. */
174 sunxi_turn_off_soc(SUNXI_SOC_A64);
175 /* Turn off the pin controller now. */
176 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
177 break;
178 case REF_DESIGN_H5:
179 sunxi_turn_off_soc(SUNXI_SOC_H5);
180
181 /*
182 * Switch PL pins to power off the board:
183 * - PL5 (VCC_IO) -> high
184 * - PL8 (PWR-STB = CPU power supply) -> low
185 * - PL9 (PWR-DRAM) ->low
186 * - PL10 (power LED) -> low
187 * Note: Clearing PL8 will reset the board, so keep it up.
188 */
189 sunxi_set_gpio_out('L', 5, 1);
190 sunxi_set_gpio_out('L', 9, 0);
191 sunxi_set_gpio_out('L', 10, 0);
192
193 /* Turn off pin controller now. */
194 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
195
196 break;
197 case AXP803_RSB:
198 /* (Re-)init RSB in case the rich OS has disabled it. */
199 sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
200 rsb_init();
201 axp_power_off();
202 break;
203 default:
204 break;
205 }
206
207 }
208