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Searched refs:neg_lo (Results 1 – 25 of 37) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
Ddl-insts.s756 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,0]
758 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,0]
760 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,1,0]
762 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,1]
764 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0]
766 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,1]
768 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,1]
784 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,0] neg_hi:[0,0,0]
786 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,0] neg_hi:[0,0,0]
788 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,1,0] neg_hi:[0,0,0]
[all …]
Dvop3p.s61 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,0,0] neg_hi:[0,0,0]
64 v_pk_fma_f16 v8, v0, s0, v1 op_sel:[0,0,0] op_sel_hi:[1,1,1] neg_lo:[0,0,0] neg_hi:[0,0,0]
80 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,1,1]
86 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,1,1] neg_hi:[1,1,1]
89 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,0,0]
92 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,1,0]
95 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,0,1]
Ddl-insts-err.s90 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo
92 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:
94 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[
96 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:]
98 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[]
100 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[,]
102 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[,0]
104 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,2]
106 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[2,0]
108 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[2,2]
[all …]
Dgfx908_err_pos.s22 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[2,0]
Dexpressions-gfx9.s47 v_pk_add_u16 v1, v2, v3 neg_lo:[2-i1,i1-1]
Dvop3p-err.s55 v_pk_add_u16 v1, v2, v3 neg_lo:[0,0]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dfmul.v2f16.ll29 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]
51 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
73 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]
148 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[1,0] neg_hi:[1,0]
149 ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[1,0] neg_hi:[1,0]
177 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
178 ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
206 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[1,1] neg_hi:[1,1]
207 ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[1,1] neg_hi:[1,1]
269 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v3 neg_lo:[1,0] neg_hi:[1,0]
[all …]
Dllvm.amdgcn.fdot2.ll44 ; GFX906-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
51 ; GFX10-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
62 ; GFX906-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
69 ; GFX10-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
80 ; GFX906-NEXT: v_dot2_f32_f16 v0, v1, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
87 ; GFX10-NEXT: v_dot2_f32_f16 v0, v1, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
Dmul.v2i16.ll27 ; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]
48 ; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
69 ; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]
Dllvm.amdgcn.sdot2.ll197 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
203 ; GFX908-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
210 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
222 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
228 ; GFX908-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
235 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
Dllvm.amdgcn.udot2.ll197 ; GFX906-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
203 ; GFX908-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
210 ; GFX10-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
222 ; GFX906-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
228 ; GFX908-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
235 ; GFX10-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
Dadd.v2i16.ll27 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]
48 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
69 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]
Dfma.ll155 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
200 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
254 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Ddl-insts.txt1090 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,0] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1093 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,1,0] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1096 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1099 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1102 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,1] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1105 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,1] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1132 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,0] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1135 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,1,0] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1138 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,1] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
1141 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] ; encoding: [0x00,0x40,0xa3,0xd3,0x01,0x05,0x…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dpacked-op-sel.ll41 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[SCALAR0]] op_sel_hi:[1,1,0] neg_lo:[0,0,1] n…
70 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[SCALAR0]] op_sel_hi:[1,1,0] neg_lo:[0,0,1] n…
129 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[SCALAR0]] op_sel_hi:[1,1,0] neg_lo:[0,0,1]{{…
184 ; GCN: v_pk_add_u16 v{{[0-9]+}}, [[VEC0]], [[SCALAR0]] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]{{$…
239 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[PACKED]] neg_lo:[0,0,1] neg_hi:[0,0,1]{{$}}
270 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] op_sel:[0,0,1] neg_lo:[0,0,1] neg_hi:…
437 …{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[0,0,1] neg_hi:[0,…
466 …_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[0,0,1]{{$}}
494 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] neg_lo:[0,0,1]{{$}}
550 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] op_sel:[0,0,1] neg_lo:[0,0,1]{{$}}
Dfsub.f16.ll92 ; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] neg_lo:[0,1] neg_hi:[0,1]
128 ; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[B_V2_F16]], [[K]] neg_lo:[1,0] neg_hi:[1,0]
Dfneg.f16.ll120 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,0] neg_hi:[1,0]{{$}}
Dstrict_fma.f16.ll143 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
Dclamp-modifier.ll223 ; GFX9: v_pk_max_f16 [[MAX:v[0-9]+]], [[ADD]], [[ADD]] neg_lo:[1,1] neg_hi:[1,1] clamp{{$}}
240 ; GFX9: v_pk_max_f16 [[MAX:v[0-9]+]], [[ADD]], [[ADD]] neg_lo:[1,1] clamp{{$}}
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX1011.rst73 …pu_synid1011_src32_1>`::ref:`f32<amdgpu_synid1011_type_dev>` :ref:`neg_lo<amdgpu_synid_neg_l…
DAMDGPUAsmGFX906.rst66 …dgpu_synid906_src32_2>`::ref:`f32<amdgpu_synid906_type_dev>` :ref:`neg_lo<amdgpu_synid_neg_l…
/external/llvm-project/llvm/docs/
DAMDGPUModifierSyntax.rst1606 neg_lo subsection
1626 … neg_lo:[{0..1}] Select affected operands for instructions with 1 source operand.
1627 … neg_lo:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
1628 … neg_lo:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
1639 neg_lo:[0]
1640 neg_lo:[0,1]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1095 def neg_lo : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
1690 neg_lo:$neg_lo, neg_hi:$neg_hi),
1694 neg_lo:$neg_lo, neg_hi:$neg_hi)),
1702 neg_lo:$neg_lo, neg_hi:$neg_hi),
1707 neg_lo:$neg_lo, neg_hi:$neg_hi))
1921 string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1141 def neg_lo : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
1682 neg_lo:$neg_lo, neg_hi:$neg_hi),
1686 neg_lo:$neg_lo, neg_hi:$neg_hi)),
1694 neg_lo:$neg_lo, neg_hi:$neg_hi),
1699 neg_lo:$neg_lo, neg_hi:$neg_hi))
1913 string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
/external/mesa3d/src/amd/compiler/
Daco_print_ir.cpp755 if (vop3->neg_lo[i] && vop3->neg_hi[i]) in aco_print_instr()
757 else if (vop3->neg_lo[i]) in aco_print_instr()

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