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Searched refs:num_render_backends (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_winsys.c37 uint32_t num_render_backends; member
129 info->num_render_backends = gpu_info[info->family].num_render_backends; in radv_null_winsys_query_info()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_binning.c47 util_logbase2_ceil(sscreen->info.num_render_backends / sscreen->info.max_se); in si_find_bin_size()
312 const unsigned num_rbs = sctx->screen->info.num_render_backends; in gfx10_get_bin_sizes()
473 if (sscreen->info.num_render_backends > 4 && ps_can_kill && db_can_reject_z_trivially && in si_emit_dpbb_state()
Dsi_query.c532 result->u32 = sctx->screen->info.num_render_backends; in si_query_sw_get_result()
681 unsigned max_rbs = screen->info.num_render_backends; in si_query_hw_prepare_buffer()
738 query->result_size = 16 * sscreen->info.num_render_backends; in si_query_hw_create()
915 fence_va = va + sctx->screen->info.num_render_backends * 16 - 8; in si_query_hw_do_emit_stop()
1183 unsigned max_rbs = sctx->screen->info.num_render_backends; in si_get_hw_query_params()
1267 unsigned max_rbs = sscreen->info.num_render_backends; in si_query_hw_add_result()
Dsi_pipe.c472 PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends, 256); in si_create_context()
476 PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends, 256); in si_create_context()
1223 if (sscreen->info.num_render_backends > 4) { in radeonsi_screen_create_impl()
Dsi_fence.c93 assert(16 * ctx->screen->info.num_render_backends <= scratch->b.b.width0); in si_cp_release_mem()
Dsi_state.c2143 const unsigned max_eqaa_samples = sscreen->info.num_render_backends == 1 ? 8 : 16; in si_is_format_supported()
5050 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16); in si_set_raster_config()
5309 if (sscreen->info.num_render_backends <= 4) { in si_init_cs_preamble_state()
/external/mesa3d/src/amd/common/
Dac_gpu_info.c540 info->num_render_backends = amdinfo->rb_pipes; in ac_query_gpu_info()
543 info->num_render_backends = 2; in ac_query_gpu_info()
547 unsigned num_rbs_per_se = info->num_render_backends / info->max_se; in ac_query_gpu_info()
733 if (info->num_render_backends == 1) in ac_query_gpu_info()
799 info->use_late_alloc = info->num_render_backends > 4; in ac_query_gpu_info()
991 fprintf(f, " num_render_backends = %i\n", info->num_render_backends); in ac_print_gpu_info()
1171 unsigned num_rb = MIN2(info->num_render_backends, 16); in ac_get_harvested_configs()
Dac_gpu_info.h192 uint32_t num_render_backends; member
/external/mesa3d/src/gallium/drivers/r600/
Dr600_query.c433 result->u32 = rctx->screen->info.num_render_backends; in r600_query_sw_get_result()
540 unsigned max_rbs = rscreen->info.num_render_backends; in r600_query_hw_prepare_buffer()
625 query->result_size = 16 * rscreen->info.num_render_backends; in r600_query_hw_create()
824 fence_va = va + ctx->screen->info.num_render_backends * 16 - 8; in r600_query_hw_do_emit_stop()
1085 unsigned max_rbs = rctx->screen->info.num_render_backends; in r600_get_hw_query_params()
1176 unsigned max_rbs = rscreen->info.num_render_backends; in r600_query_hw_add_result()
1851 ctx->screen->info.num_render_backends = 8; in r600_query_fix_enabled_rb_mask()
1853 max_rbs = ctx->screen->info.num_render_backends; in r600_query_fix_enabled_rb_mask()
2126 if (((struct r600_common_screen*)rctx->b.screen)->info.num_render_backends > 0) in r600_query_init()
Dr600_pipe_common.c1352 printf("num_render_backends = %i\n", rscreen->info.num_render_backends); in r600_common_screen_init()
/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c407 &ws->info.num_render_backends)) in do_winsys_init()
447 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends); in do_winsys_init()
/external/mesa3d/src/amd/vulkan/
Dradv_query.c169 unsigned db_count = device->physical_device->rad_info.num_render_backends; in build_occlusion_query_shader()
1171 pool->stride = 16 * device->physical_device->rad_info.num_render_backends; in radv_CreateQueryPool()
1277 uint32_t db_count = device->physical_device->rad_info.num_render_backends; in radv_GetQueryPoolResults()
Dsi_cmd_buffer.c157 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16); in si_set_raster_config()
429 if (physical_device->rad_info.num_render_backends <= 4) { in si_emit_graphics()
Dradv_pipeline.c3716 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends / in radv_gfx9_compute_bin_size()
3784 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends; in radv_gfx10_compute_bin_size()
3911 if (pdev->rad_info.num_render_backends > 4) { in radv_get_binning_settings()
Dradv_cmd_buffer.c443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends; in radv_reset_cmd_buffer()
/external/mesa3d/docs/relnotes/
D20.1.0.rst3930 - radv/winsys: spoof some values for num_render_backends in the null