1 /*
2 * Copyright © 2020 Valve Corporation
3 *
4 * based on amdgpu winsys.
5 * Copyright © 2016 Red Hat.
6 * Copyright © 2016 Bas Nieuwenhuizen
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27 #include "radv_null_winsys_public.h"
28
29 #include "radv_null_bo.h"
30 #include "radv_null_cs.h"
31
32 #include "ac_llvm_util.h"
33
34 /* Hardcode some GPU info that are needed for the driver or for some tools. */
35 static const struct {
36 uint32_t pci_id;
37 uint32_t num_render_backends;
38 } gpu_info[] = {
39 [CHIP_TAHITI] = { 0x6780, 8 },
40 [CHIP_PITCAIRN] = { 0x6800, 8, },
41 [CHIP_VERDE] = { 0x6820, 4 },
42 [CHIP_OLAND] = { 0x6060, 2 },
43 [CHIP_HAINAN] = { 0x6660, 2 },
44 [CHIP_BONAIRE] = { 0x6640, 4 },
45 [CHIP_KAVERI] = { 0x1304, 2 },
46 [CHIP_KABINI] = { 0x9830, 2 },
47 [CHIP_HAWAII] = { 0x67A0, 16 },
48 [CHIP_TONGA] = { 0x6920, 8 },
49 [CHIP_ICELAND] = { 0x6900, 2 },
50 [CHIP_CARRIZO] = { 0x9870, 2 },
51 [CHIP_FIJI] = { 0x7300, 16 },
52 [CHIP_STONEY] = { 0x98E4, 2 },
53 [CHIP_POLARIS10] = { 0x67C0, 8 },
54 [CHIP_POLARIS11] = { 0x67E0, 4 },
55 [CHIP_POLARIS12] = { 0x6980, 4 },
56 [CHIP_VEGAM] = { 0x694C, 4 },
57 [CHIP_VEGA10] = { 0x6860, 16 },
58 [CHIP_VEGA12] = { 0x69A0, 8 },
59 [CHIP_VEGA20] = { 0x66A0, 16 },
60 [CHIP_RAVEN] = { 0x15DD, 2 },
61 [CHIP_RENOIR] = { 0x1636, 2 },
62 [CHIP_ARCTURUS] = { 0x738C, 2 },
63 [CHIP_NAVI10] = { 0x7310, 16 },
64 [CHIP_NAVI12] = { 0x7360, 8 },
65 [CHIP_NAVI14] = { 0x7340, 8 },
66 /* TODO: fill with real info. */
67 [CHIP_SIENNA_CICHLID] = { 0xffff, 8 },
68 [CHIP_NAVY_FLOUNDER] = { 0xffff, 8 },
69 };
70
radv_null_winsys_query_info(struct radeon_winsys * rws,struct radeon_info * info)71 static void radv_null_winsys_query_info(struct radeon_winsys *rws,
72 struct radeon_info *info)
73 {
74 const char *family = getenv("RADV_FORCE_FAMILY");
75 unsigned i;
76
77 info->chip_class = CLASS_UNKNOWN;
78 info->family = CHIP_UNKNOWN;
79
80 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
81 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
82 /* Override family and chip_class. */
83 info->family = i;
84 info->name = "OVERRIDDEN";
85
86 if (i >= CHIP_SIENNA_CICHLID)
87 info->chip_class = GFX10_3;
88 else if (i >= CHIP_NAVI10)
89 info->chip_class = GFX10;
90 else if (i >= CHIP_VEGA10)
91 info->chip_class = GFX9;
92 else if (i >= CHIP_TONGA)
93 info->chip_class = GFX8;
94 else if (i >= CHIP_BONAIRE)
95 info->chip_class = GFX7;
96 else
97 info->chip_class = GFX6;
98 }
99 }
100
101 if (info->family == CHIP_UNKNOWN) {
102 fprintf(stderr, "radv: Unknown family: %s\n", family);
103 abort();
104 }
105
106 info->pci_id = gpu_info[info->family].pci_id;
107 info->has_syncobj_wait_for_submit = true;
108 info->max_se = 4;
109 info->num_se = 4;
110 if (info->chip_class >= GFX10_3)
111 info->max_wave64_per_simd = 16;
112 else if (info->chip_class >= GFX10)
113 info->max_wave64_per_simd = 20;
114 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
115 info->max_wave64_per_simd = 8;
116 else
117 info->max_wave64_per_simd = 10;
118
119 if (info->chip_class >= GFX10)
120 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
121 else if (info->chip_class >= GFX8)
122 info->num_physical_sgprs_per_simd = 800;
123 else
124 info->num_physical_sgprs_per_simd = 512;
125
126 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
127 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
128 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
129 info->num_render_backends = gpu_info[info->family].num_render_backends;
130 }
131
radv_null_winsys_destroy(struct radeon_winsys * rws)132 static void radv_null_winsys_destroy(struct radeon_winsys *rws)
133 {
134 FREE(rws);
135 }
136
137 struct radeon_winsys *
radv_null_winsys_create()138 radv_null_winsys_create()
139 {
140 struct radv_null_winsys *ws;
141
142 ws = calloc(1, sizeof(struct radv_null_winsys));
143 if (!ws)
144 return NULL;
145
146 ws->base.destroy = radv_null_winsys_destroy;
147 ws->base.query_info = radv_null_winsys_query_info;
148 radv_null_bo_init_functions(ws);
149 radv_null_cs_init_functions(ws);
150
151 return &ws->base;
152 }
153